公开(公告)号：US10686031B2

公开(公告)日：2020-06-16

申请号：US15937097

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Peijie Feng ,  Junjing Bao ,  Ye Lu ,  Giridhar Nallapati

IPC: H01L49/02 ,  H01L23/522

Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.

公开(公告)号：US10651122B1

公开(公告)日：2020-05-12

申请号：US16278539

申请日：2019-02-18

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) interconnect structure may include a metal layer with asymmetric metal line-dielectric structures supporting fully self-aligned vertical interconnect accesses (vias). The interconnect structure includes metal lines spaced at a metal line pitch and dielectric structures disposed between adjacent metal lines. The width of the metal lines is asymmetric to the width of dielectric structures, providing an asymmetric width relationship that allows a metal line to have a greater cross-sectional area for reducing electrical resistance without having to increase metal line pitch. The via pattern is self-aligned to an upper metal opening at the top and an underlayer metal recess opening at the bottom, allowing the maximum contact area to reduce via resistance. To reduce capacitive coupling between adjacent metal lines, the adjacent interconnect structures include a plurality of gaps formed in a dielectric material of the dielectric structure.

公开(公告)号：US20170338215A1

公开(公告)日：2017-11-23

申请号：US15160992

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Giridhar Nallapati ,  Da Yang ,  Kern Rim ,  Robert Bucki ,  Choh Fei Yeap

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/11803 ,  H01L28/00 ,  H01L2027/11809 ,  H01L2027/11824 ,  H01L2027/11874 ,  H01L2027/11881

Abstract: A heterogeneous cell array includes a first column of cells and a second column of cells. The first column of cells includes a first cell having a first area and a second cell having the first area. The first cell includes two fin-type field effect transistors having a first number of fins and the second cell includes two fin-type field effect transistors having the first number of fins. The second column of cells includes a third cell having a second area. The third cell is adjacent to the first cell and to the second cell, and the third cell includes two fin-type field effect transistors having a second number of fins. The second area is greater than the first area, and the second number of fins is greater than the first number of fins.

公开(公告)号：US09024418B2

公开(公告)日：2015-05-05

申请号：US13829864

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Giridhar Nallapati ,  PR Chidambaram

IPC: H01L27/02 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L23/528 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect.

Abstract translation: 提供局部互连结构，其包括通过扩散导向的局部互连耦合到相邻栅极层的栅极定向局部互连。

公开(公告)号：US20240203866A1

公开(公告)日：2024-06-20

申请号：US18590242

申请日：2024-02-28

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Junjing Bao ,  Giridhar Nallapati

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/13 ,  H01L2224/13025

Abstract: Integrated circuits (ICs), including capacitors and inductors, employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related fabrication methods. By directly coupled, it is meant that there is not an intermediate vertical interconnect access (via) layer with a via(s) interconnecting the metal lines in vertically-adjacent interconnect layers. An overlying and underlying metal line in respective and vertically-adjacent overlying and underlying interconnect layers are directly coupled to each other without the need for an intermediate via layer.
For example, directly coupled metal in adjacent interconnect layers of IC can reduce contact resistance between the metal lines and reduce the overall height of the IC. An insulating layer(s) can be disposed in select recessed regions between the overlying interconnect layer and the underlying interconnect layer to insulate an overlying metal line from another vertically-intersecting underlying metal line that are not intended to be electrically coupled together.

公开(公告)号：US11942414B2

公开(公告)日：2024-03-26

申请号：US17478539

申请日：2021-09-17

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Junjing Bao ,  Giridhar Nallapati

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/13 ,  H01L2224/13025

Abstract: Integrated circuits (ICs), including capacitors and inductors, employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related fabrication methods. By directly coupled, it is meant that there is not an intermediate vertical interconnect access (via) layer with a via(s) interconnecting the metal lines in vertically-adjacent interconnect layers. An overlying and underlying metal line in respective and vertically-adjacent overlying and underlying interconnect layers are directly coupled to each other without the need for an intermediate via layer. For example, directly coupled metal in adjacent interconnect layers of IC can reduce contact resistance between the metal lines and reduce the overall height of the IC. An insulating layer(s) can be disposed in select recessed regions between the overlying interconnect layer and the underlying interconnect layer to insulate an overlying metal line from another vertically-intersecting underlying metal line that are not intended to be electrically coupled together.

公开(公告)号：US20240096964A1

公开(公告)日：2024-03-21

申请号：US17933568

申请日：2022-09-20

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Xia Li ,  Giridhar Nallapati

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/40 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7848

Abstract: Vertical channel field-effect transistors (VCFETs) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods. In exemplary aspects, to reduce contact resistance of the VCFET, an end portion of the vertical channel has a semiconductor structure that has an expanded width in the horizontal direction parallel to the substrate surface. This provides a greater area to form a contact for a source/drain to reduce contact resistance of the VCFET. To reduce the parasitic capacitance between the gate and a contact of the VCFET, the spacer includes one or more air gaps that form an air spacer(s) between the gate and the contact to reduce the overall average permittivity of the spacer. In one example, the air spacer(s) of the VCFET is elongated in the horizontal direction parallel to the substrate surface (and perpendicular to the vertical direction of the vertical channel) to further reduce the parasitic capacitance.

公开(公告)号：US20240079352A1

公开(公告)日：2024-03-07

申请号：US17929408

申请日：2022-09-02

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  Lily Zhao ,  Dongming He

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/642 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16235 ,  H01L2224/17163 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/19041 ,  H01L2924/30101 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: Aspects disclosed herein include integrated circuit (IC) packages employing a capacitor interposer substrate with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies (“dies”) electrically coupled to a package substrate that supports electrical signal routing to and from the die(s). The capacitor interposer substrate is disposed between the die(s) and the package substrate. The die(s) is coupled to embedded capacitor(s) in the capacitor interposer substrate through die interconnects coupled to external interconnects of the capacitor interposer substrate. In exemplary aspects, the external interconnects on the outer surfaces of the capacitor interposer substrate are aligned. In this manner, the capacitor interposer substrate can maintain interconnect compatibility to the die(s) and package substrate if the die(s) and package substrate have a pattern of die interconnects and external interconnects that are designed to align with each other when coupled to each other.

公开(公告)号：US20220375851A1

公开(公告)日：2022-11-24

申请号：US17324614

申请日：2021-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Stanley Seungchul Song ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L49/02

Abstract: Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed on an IC, in an ILM, to minimize the lengths of the power and ground traces coupling the DTCs to circuits in a semiconductor layer. The DTCs and the semiconductor layer are on opposite sides of the metal layer(s) used to interconnect the circuits, so the locations of the DTCs in the ILM can be independent of circuit layout and interconnect routing. IC dies with DTCs disposed in the ILM can significantly reduce voltage droop and spikes in IC dies in an IC stack. In one example, DTCs are also located in trenches in the substrate of the IC die.

公开(公告)号：US11437379B2

公开(公告)日：2022-09-06

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Deepak Sharma ,  Bharani Chava ,  Hyeokjin Lim ,  Peijie Feng ,  Seung Hyuk Kang ,  Jonghae Kim ,  Periannan Chidambaram ,  Kern Rim ,  Giridhar Nallapati ,  Venugopal Boynapalli ,  Foua Vang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/095 ,  H01L23/528 ,  H01L29/78 ,  H03K19/0185

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.