公开(公告)号：US20180061766A1

公开(公告)日：2018-03-01

申请号：US15249143

申请日：2016-08-26

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI

IPC: H01L23/538 ,  H01L27/092 ,  H01L27/12 ,  H01L23/66 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/78 ,  H04W88/02

Abstract: An integrated circuit device includes only semiconductor devices with a same first polarity on one side of an insulator layer and only semiconductor devices with a different second polarity on an opposite side of the insulator layer to reduce size and complexity of the integrated circuit device as well as reducing the process steps associated with fabricating the integrated circuit device. Shared contacts between backside source/drain regions or spacers of the semiconductor devices with the first polarity and front-side source/drain regions or spacers of the semiconductor devices with the first polarity are used to connect the semiconductor devices on opposite sides of the insulator layer.

公开(公告)号：US20210242127A1

公开(公告)日：2021-08-05

申请号：US16779192

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Farid AZZAZY ,  Ravi Pramod Kumar VEDULA

IPC: H01L23/522 ,  H01L49/02

Abstract: An integrated circuit (IC) is described. The IC includes a substrate and a plurality of back-end-of-line (BEOL) layers on the substrate. The IC also includes a trench having tapered sidewalls and a base in a BEOL layer of the plurality of BEOL layers on the substrate. The IC further includes a metal-insulator-metal (MIM) capacitor on the tapered sidewalls and the base of the trench in the BEOL layer. The MIM capacitor includes a first conductive layer to line the tapered sidewalls and the base of the trench. The MIM capacitor also includes a dielectric layer to line the first conductive layer on the tapered sidewalls and the base of the trench. The MIM capacitor further includes a second conductive layer on the dielectric layer and filling the trench in the BEOL layer.

公开(公告)号：US20200075633A1

公开(公告)日：2020-03-05

申请号：US16115352

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Stephen Alan FANELLI ,  Sinan GOKTEPELI

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/51 ,  H01L29/06

Abstract: An integrated circuit device includes a portion of a support wafer (e.g., a handle wafer), silicon on insulator layer, a first active device, and a second active device. The first active device has a first semiconductor thickness in a dielectric layer (e.g., a buried oxide layer). The first active device is on the SOI layer. The second active device has a second semiconductor thickness in the same dielectric layer as the first active device. The supporting wafer supports the first active device and the second active device. The second active device is also on the SOI layer. The first and second thicknesses are different from one another.

公开(公告)号：US20190386121A1

公开(公告)日：2019-12-19

申请号：US16011430

申请日：2018-06-18

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  George Pete IMTHURN ,  Stephen Alan FANELLI

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: A heterojunction bipolar transistor is integrated on radio frequency (RF) dies of different sizes. The heterojunction bipolar transistor includes an emitter on a first-side of a semiconductor-on-insulator (SOI) layer of an SOI substrate. The emitter is accessed from the first-side while a collector is accessed from a second-side of the SOI substrate. One or more portions of a base of the heterojunction bipolar transistor is between the emitter and one or more portions of the collector. The heterojunction bipolar transistor also includes a compound semiconductor layer between the collector and the emitter. The compound semiconductor layer carries a charge between the emitter and the collector.

公开(公告)号：US20190326448A1

公开(公告)日：2019-10-24

申请号：US15957484

申请日：2018-04-19

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Fabio Alessio MARINO ,  Narasimhulu KANIKE ,  Plamen Vassilev KOLEV ,  Qingqing LIANG ,  Paolo MENEGOLI ,  Francesco CAROBOLANTE ,  Aristotele HADJICHRISTOS

IPC: H01L29/93 ,  H01L29/45 ,  H01L29/06

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.

公开(公告)号：US20190109152A1

公开(公告)日：2019-04-11

申请号：US16000501

申请日：2018-06-05

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  Sinan GOKTEPELI ,  Jarred MOORE

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/66

Abstract: A radio frequency integrated circuit (RFIC) is described. The RFIC includes a switch field effect transistor (FET), including a source region, a drain region, a body region, and a gate. The RFIC also includes a body bypass resistor coupled between the gate and the body region. The RFIC further includes a gate isolation resistor coupled between the gate and the body region. The RFIC also includes a diode coupled between the body bypass resistor and the gate isolation resistor.

公开(公告)号：US20190097592A1

公开(公告)日：2019-03-28

申请号：US15976710

申请日：2018-05-10

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI

IPC: H03F3/193 ,  H03F3/21 ,  H01L27/088 ,  H04B15/00 ,  H04B1/04

CPC classification number: H03F3/193 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H03F3/195 ,  H03F3/21 ,  H03F3/245 ,  H03F3/68 ,  H03F2200/294 ,  H04B1/006 ,  H04B1/0064 ,  H04B1/04 ,  H04B1/525 ,  H04B15/005

Abstract: A low noise amplifier (LNA) device includes a first transistor on a semiconductor on insulator (SOI) layer. The first transistor includes a source region, a drain region, and a gate. The LNA device also includes a first-side gate contact coupled to the gate. The LNA device further includes a second-side source contact coupled to the source region. The LNA device also includes a second-side drain contact coupled to the drain region.

公开(公告)号：US20180175034A1

公开(公告)日：2018-06-21

申请号：US15387501

申请日：2016-12-21

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Jean RICHAUD

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0694 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42392

Abstract: An integrated circuit device may include a p-type metal oxide semiconductor (PMOS) transistor supported by a backside of an isolation layer. The integrated circuit device may also include an n-type metal oxide semiconductor (NMOS) transistor supported by a front-side of the isolation layer, opposite the backside. The integrated circuit device may further include a shared contact extending through the isolation layer and electrically coupling a first terminal of the PMOS transistor to the first terminal of the NMOS transistor.

公开(公告)号：US20180076145A1

公开(公告)日：2018-03-15

申请号：US15266972

申请日：2016-09-15

Applicant: Qualcomm Incorporated

Inventor： Sinan GOKTEPELI

IPC: H01L23/544 ,  H01L27/12 ,  H01L21/683 ,  H01L21/84 ,  H01L21/762 ,  H01L27/13

CPC classification number: H01L23/544 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0694 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/1266 ,  H01L27/13 ,  H01L2221/6835

Abstract: An integrated circuit structure may include an alignment column on a front-side surface of an isolation layer. The alignment column may extend through a backside surface opposite the front-side surface of the isolation layer. The integrated circuit structure may also include front-side transistors on the front-side surface of the isolation layer. The integrated circuit structure may further include backside transistors on the backside surface of the isolation layer. A first front-side transistor is aligned with a first backside transistor according to the alignment column.

公开(公告)号：US20200044621A1

公开(公告)日：2020-02-06

申请号：US16050212

申请日：2018-07-31

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan FANELLI ,  Sinan GOKTEPELI ,  Alexandre Augusto SHIRAKAWA

IPC: H03H3/10 ,  H03H9/02 ,  H01L41/312 ,  H01L41/338

Abstract: In certain aspects, a thin film surface acoustic wave (SAW) die comprises a high-resistivity substrate, a bonding layer on the high-resistivity substrate, and a thin film piezoelectric island on the bonding layer, where an edge of the thin film piezoelectric island is offset from an edge of the bonding layer.