公开(公告)号：US11544145B2

公开(公告)日：2023-01-03

申请号：US17363622

申请日：2021-06-30

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F11/10

Abstract: A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.

公开(公告)号：US11527302B2

公开(公告)日：2022-12-13

申请号：US17368018

申请日：2021-07-06

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/00 ,  G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/52

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US20220283941A1

公开(公告)日：2022-09-08

申请号：US17702505

申请日：2022-03-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US11379392B2

公开(公告)日：2022-07-05

申请号：US16942380

申请日：2020-07-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US11323118B1

公开(公告)日：2022-05-03

申请号：US17007232

申请日：2020-08-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03K19/0944 ,  H03K19/20

Abstract: A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.

公开(公告)号：US11301378B2

公开(公告)日：2022-04-12

申请号：US16652234

申请日：2018-10-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12 ,  G11C14/00

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US20220101912A1

公开(公告)日：2022-03-31

申请号：US17501311

申请日：2021-10-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US11264085B1

公开(公告)日：2022-03-01

申请号：US16927892

申请日：2020-07-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G06F12/14 ,  G11C11/408 ,  G11C11/4072 ,  G11C29/38 ,  G11C29/32 ,  G11C29/22 ,  G11C7/10 ,  G11C5/04

Abstract: In a memory component having a page buffer with 2N independently accessible regions, N bits of a command/address value are decoded to access contents within a first one of the 2N page-buffer regions if a configuration value specifies a first addressing resolution and, if the configuration value specifies a second addressing resolution, a composite address that includes fewer than N bits of the command/address value together with a plurality of bits generated within the memory component to access contents within a second one of the 2N page-buffer regions.

公开(公告)号：US10726901B1

公开(公告)日：2020-07-28

申请号：US16528514

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G11C11/40 ,  G11C11/402 ,  G11C11/409 ,  G11C5/06

Abstract: A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.

公开(公告)号：US10706913B2

公开(公告)日：2020-07-07

申请号：US16261937

申请日：2019-01-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.