公开(公告)号：US20220210364A1

公开(公告)日：2022-06-30

申请号：US17540925

申请日：2021-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Fukashi MORISHITA

IPC: H04N5/3745 ,  H04N5/378

Abstract: It is an object of the present invention to provide a technique for reducing the variation of a bias voltage.
An analog-to-digital converter comprises a comparator including a first amplifier and a second amplifier inputted one output of the first amplifier. The first amplifier is a differential type of amplifier, and includes one input terminal for receiving a signal and the other input terminal for receiving a reference signal which changes with a predetermined slope. The second amplifier is a single-ended type amplifier, and determines an auto zero voltage based on the amplified voltage by an auto zero operation of the first amplifier and includes a self-bias circuit using the auto zero voltage as a bias voltage. The comparator is plural, the comparators are plurality which arranged in a row direction, and outputs a digital value based on an analog voltage inputted to the other input terminal in parallel operation.

公开(公告)号：US20160249005A1

公开(公告)日：2016-08-25

申请号：US14961603

申请日：2015-12-07

Applicant: Renesas Electronics Corporation

Inventor： Osamu MATSUMOTO ,  Fukashi MORISHITA

IPC: H04N5/3745 ,  H04N5/63 ,  H04N5/378

CPC classification number: H04N5/378 ,  H04N5/3658

Abstract: In a CMOS image sensor, a plurality of bias circuits are dispersedly arranged in an arrangement region of column circuits corresponding to each column of a pixel array. Each bias circuit generates a bias voltage on the basis of a reference current which has been input and supplies the generated bias voltage to the corresponding column circuit 10 which is arranged in the vicinity. Thereby, luminance unevenness of a picked-up image caused by an IR drop of a ground wire for the column circuits is reduced.

Abstract translation: 在CMOS图像传感器中，多个偏置电路分散布置在与像素阵列的每列对应的列电路的布置区域中。 每个偏置电路基于已经输入的参考电流产生偏置电压，并将产生的偏置电压提供给布置在附近的对应的列电路10。 由此，降低了由列电路的接地线的IR下降引起的拍摄图像的亮度不均匀性。

公开(公告)号：US20160248999A1

公开(公告)日：2016-08-25

申请号：US14962744

申请日：2015-12-08

Applicant: Renesas Electronics Corporation

Inventor： Kazuhiro UEDA ,  Fukashi MORISHITA

IPC: H04N5/378 ,  H04N5/372 ,  H04N5/374 ,  H04N5/369

CPC classification number: H04N5/378 ,  H04N5/347 ,  H04N5/37457

Abstract: The present invention is directed to solve a problem that, in an imaging element, complicated control is necessary for reading data for focus detection. A scanning circuit makes a first signal output from a pixel by setting first and second switches to “off” in a period before a first timing, makes a second signal output from the pixel by setting only the first switch to “on” for a predetermined period from the first timing, and makes a third signal output from the pixel by setting the first and second switches to “on” for a predetermined period from a second timing after the first timing. A first AD converter performs AD conversion by comparing the difference between the second signal and the first signal with a reference signal. A second AD converter performs AD conversion by comparing the difference between a third signal and the second signal with the reference signal.

Abstract translation: 本发明旨在解决在成像元件中需要复杂的控制来读取用于焦点检测的数据的问题。 扫描电路通过在第一定时之前的周期内将第一和第二开关设置为“关闭”来从像素输出第一信号，通过将第一开关仅设置为“接通”来预定第二信号，从而从第一定时输出第二信号 并且通过将第一和第二开关从第一定时之后的第二定时设置为“接通”一段预定时间段，从而从像素输出第三信号。 第一AD转换器通过用参考信号比较第二信号和第一信号之间的差来执行AD转换。 第二AD转换器通过将第三信号和第二信号之间的差与参考信号进行比较来执行AD转换。

公开(公告)号：US20150312506A1

公开(公告)日：2015-10-29

申请号：US14691848

申请日：2015-04-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunsuke OKURA ,  Fukashi MORISHITA

IPC: H04N5/3745 ,  H01L27/146

CPC classification number: H04N5/37457 ,  H01L27/14641 ,  H01L27/14643 ,  H04N5/378

Abstract: The present invention makes it possible to read a pixel signal at high speed. A pixel array includes a plurality of pixels that store an electrical charge. The amount of stored electrical charge is based on the amount of received light. A first pixel current source and a second pixel current source are coupled in parallel between a ground voltage and a pixel output node on a pixel signal read line. A switch is disposed in a wiring path that couples the pixel output node, the second pixel current source, and the ground voltage.

Abstract translation: 本发明使得可以高速读取像素信号。 像素阵列包括存储电荷的多个像素。 存储的电荷量基于所接收的光量。 第一像素电流源和第二像素电流源并联耦合在像素信号读取线上的接地电压和像素输出节点之间。 开关设置在连接像素输出节点，第二像素电流源和接地电压的布线路径中。

公开(公告)号：US20150228341A1

公开(公告)日：2015-08-13

申请号：US14691125

申请日：2015-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naoya WATANABE ,  Isamu HAYASHI ,  Teruhiko AMANO ,  Fukashi MORISHITA ,  Kenji YOSHINAGA ,  Mihoko AKIYAMA ,  Shinya MIYAZAKI ,  Masakazu ISHIBASHI ,  Katsumi DOSAKA

IPC: G11C15/04

CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US20150124138A1

公开(公告)日：2015-05-07

申请号：US14518073

申请日：2014-10-20

Applicant: Renesas Electronics Corporation

Inventor： Kazuhiro UEDA ,  Shunsuke OKURA ,  Fukashi MORISHITA

IPC: H04N5/3745 ,  H04N5/376

CPC classification number: H04N5/378 ,  H03M1/00 ,  H03M1/66 ,  H04N5/3575 ,  H04N5/37455 ,  H04N5/376

Abstract: Provided is a solid-state image sensing device that performs an A/D conversion operation at high speed. A sample-and-hold section 12 included in an A/D converter in a CMOS image sensor includes switches S1a and S1b and capacitor C1 that sample and hold a dark signal during each cycle period, switches S2a and S2b and capacitor C2 that sample and hold a bright signal during an odd-numbered cycle period, and switches S3a and S3b and capacitor C3 that sample and hold a bright signal during an even-numbered cycle period. While a bright signal is held with switch S2b placed in a conducting state, the next bright signal can be sampled by placing switch S3a in a conducting state.

Abstract translation: 提供一种以高速执行A / D转换操作的固态图像感测装置。 包括在CMOS图像传感器中的A / D转换器中的采样保持部分12包括开关S1a和S1b以及在每个周期期间采样和保持暗信号的电容器C1，开关S2a和S2b以及电容器C2， 在奇数周期期间保持亮信号，并且在偶数周期期间切换S3a和S3b以及采样并保持亮信号的电容器C3。 当开关S2b置于导通状态下保持亮信号时，可以通过将开关S3a置于导通状态来对下一个亮信号进行采样。