公开(公告)号：US20170345755A1

公开(公告)日：2017-11-30

申请号：US15479978

申请日：2017-04-05

申请人： Renesas Electronics Corporation

发明人： Shinichi UCHIDA ,  Keiichiro TANAKA ,  Takafumi KURAMOTO

IPC分类号： H01L23/522 ,  H01L23/552 ,  H01L23/532 ,  H01L23/528 ,  G01R19/00 ,  G01R15/18 ,  H01L21/3205 ,  H01F41/04 ,  H01F27/34 ,  H01F27/28 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L23/5227 ,  G01R15/18 ,  G01R15/181 ,  G01R19/0092 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/34 ,  H01F41/041 ,  H01F2017/0073 ,  H01F2017/008 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/76224 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L23/552 ,  H01L29/0649

摘要： According to one embodiment, a semiconductor device 1 includes an Si substrate 11, an inductor 12 formed in wiring layers disposed above the Si substrate 11, and a shield 13 formed so as to surround the inductor 12, in which the shield 13 includes metals 105 to 109 formed in, among the wiring layers, a layer in which the inductor 12 is formed and a layer above that layer, and a silicide 104 formed between the Si substrate 11 and the wiring layers above the Si substrate 11.

公开(公告)号：US20160118368A1

公开(公告)日：2016-04-28

申请号：US14989661

申请日：2016-01-06

申请人： Renesas Electronics Corporation

发明人： Shinpei WATANABE ,  Shinichi UCHIDA ,  Tadashi MAEDA ,  Shigeru TANAKA

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/3185 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/62 ,  H01L23/645 ,  H01L24/32 ,  H01L24/73 ,  H01L27/0617 ,  H01L27/0922 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2924/1206 ,  H01L2924/181 ,  H01L2924/19042 ,  H04B5/005 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first external connection terminal formed on the first main surface; a second semiconductor chip that includes a second main surface, a second inductor formed on the second main surface, a second external connection terminal formed on the second main surface; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other such that the first main surface and the second main face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view.

摘要翻译： 半导体器件包括：第一半导体芯片，包括第一主表面，形成在第一主表面上的第一电感器和形成在第一主表面上的第一外部连接端子; 第二半导体芯片，包括第二主表面，形成在第二主表面上的第二电感器，形成在第二主表面上的第二外部连接端子; 以及位于所述第一半导体芯片和所述第二半导体芯片之间的第一绝缘膜，其中所述第一半导体芯片和所述第二半导体芯片彼此重叠，使得所述第一主表面和所述第二主面彼此相对，所述半导体器件包括 当在平面图中看到第一半导体芯片和第二半导体芯片彼此重叠时的面对区域。

公开(公告)号：US20160111357A1

公开(公告)日：2016-04-21

申请号：US14982155

申请日：2015-12-29

申请人： Renesas Electronics Corporation

发明人： Shinichi UCHIDA ,  Kenji NISHIKAWA ,  Masato KANNO ,  Mika YONEZAWA ,  Shunichi KAERIYAMA ,  Toshinori KIYOHARA

IPC分类号： H01L23/495 ,  H01L49/02

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49551 ,  H01L23/5227 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L28/10 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/29034 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32135 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48249 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/743 ,  H01L2224/75745 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.