公开(公告)号：US20180041233A1

公开(公告)日：2018-02-08

申请号：US15727968

申请日：2017-10-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi TAKEDA ,  Hirokazu NAGASE ,  Shinpei WATANABE

IPC: H04B1/04 ,  H04L25/02 ,  H01L23/60 ,  H04B1/40 ,  H04L1/00 ,  H04B5/00

CPC classification number: H04B1/04 ,  H01L23/60 ,  H01L2924/16152 ,  H04B1/40 ,  H04B5/0012 ,  H04B5/0075 ,  H04B5/0081 ,  H04L1/0041 ,  H04L25/0266

Abstract: The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

公开(公告)号：US20160277043A1

公开(公告)日：2016-09-22

申请号：US15066900

申请日：2016-03-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi TAKEDA ,  Hirokazu NAGASE ,  Shinpei WATANABE

IPC: H04B1/04 ,  H04B1/40 ,  H01L23/60

CPC classification number: H04B1/04 ,  H01L23/60 ,  H01L2924/16152 ,  H04B1/40 ,  H04B5/0012 ,  H04B5/0075 ,  H04B5/0081 ,  H04L1/0041 ,  H04L25/0266

Abstract: The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

Abstract translation: 根据一个实施例的发射机电路包括基于输入数据的边缘产生脉冲信号的脉冲发生电路，第一输出驱动器基于脉冲信号将根据其中一个边缘的第一输出脉冲信号输出到第一端 的第二输出驱动器，所述第二输出驱动器基于所述脉冲信号将根据所述边缘中的另一个的第二输出脉冲信号输出到所述绝缘耦合元件的第二端，以及输出停止电路，其将所述第一和 第二输出脉冲信号从电源电压接通开始输出规定的时间段。

公开(公告)号：US20180301978A1

公开(公告)日：2018-10-18

申请号：US15900949

申请日：2018-02-21

Applicant: Renesas Electronics Corporation

Inventor： Shinpei WATANABE

IPC: H02M1/088 ,  H02P5/00 ,  H03K17/56

CPC classification number: H02M1/088 ,  H02M1/32 ,  H02M7/5387 ,  H02M2001/0003 ,  H02M2001/008 ,  H02P5/00 ,  H02P5/68 ,  H02P7/04 ,  H03K17/56

Abstract: A semiconductor device includes a plurality of H-bridge circuits and a logic circuit which is commonly used for the plurality of H-bridge circuits. The logic circuit controls driving of each of the plurality of H-bridge circuits on the basis of signals which are input thereinto in such a manner that a combination of respective driving states of the plurality of H-bridge circuits meets a predetermined condition.

公开(公告)号：US20160118368A1

公开(公告)日：2016-04-28

申请号：US14989661

申请日：2016-01-06

Applicant: Renesas Electronics Corporation

Inventor： Shinpei WATANABE ,  Shinichi UCHIDA ,  Tadashi MAEDA ,  Shigeru TANAKA

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/62 ,  H01L23/645 ,  H01L24/32 ,  H01L24/73 ,  H01L27/0617 ,  H01L27/0922 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2924/1206 ,  H01L2924/181 ,  H01L2924/19042 ,  H04B5/005 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first external connection terminal formed on the first main surface; a second semiconductor chip that includes a second main surface, a second inductor formed on the second main surface, a second external connection terminal formed on the second main surface; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other such that the first main surface and the second main face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view.

Abstract translation: 半导体器件包括：第一半导体芯片，包括第一主表面，形成在第一主表面上的第一电感器和形成在第一主表面上的第一外部连接端子; 第二半导体芯片，包括第二主表面，形成在第二主表面上的第二电感器，形成在第二主表面上的第二外部连接端子; 以及位于所述第一半导体芯片和所述第二半导体芯片之间的第一绝缘膜，其中所述第一半导体芯片和所述第二半导体芯片彼此重叠，使得所述第一主表面和所述第二主面彼此相对，所述半导体器件包括 当在平面图中看到第一半导体芯片和第二半导体芯片彼此重叠时的面对区域。

公开(公告)号：US20170148751A1

公开(公告)日：2017-05-25

申请号：US15424059

申请日：2017-02-03

Applicant: Renesas Electronics Corporation

Inventor： Shinpei WATANABE ,  Shinichi Uchida ,  Tadashi Maeda ,  Kazuo Henmi

IPC: H01L23/64 ,  H01F38/14 ,  H01L23/495 ,  H01L23/31 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/162 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06527 ,  H01L2924/13055 ,  H01L2924/181 ,  H04B5/0031 ,  H04B5/0081 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01014

Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.

公开(公告)号：US20160093570A1

公开(公告)日：2016-03-31

申请号：US14863264

申请日：2015-09-23

Applicant: Renesas Electronics Corporation

Inventor： Shinpei WATANABE ,  Shinichi UCHIDA ,  Tadashi MAEDA ,  Kazuo HENMI

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/528 ,  H01L23/31 ,  H01L25/065 ,  H04B5/00

CPC classification number: H01L23/645 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/162 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06527 ,  H01L2924/13055 ,  H01L2924/181 ,  H04B5/0031 ,  H04B5/0081 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01014

Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.

Abstract translation: 在相对的两个半导体芯片之间防止介电击穿，以提高半导体器件的可靠性。 第一半导体芯片具有包括多个布线层的布线结构，在布线结构中形成的第一线圈和形成在布线结构上的绝缘膜。 第二半导体芯片具有包括多个布线层的布线结构，形成在布线结构上的第二线圈和形成在布线结构上的绝缘膜。 第一半导体芯片和第二半导体芯片通过绝缘片与第一半导体芯片的绝缘膜和第二半导体芯片的绝缘膜彼此面对而堆叠。 第一线圈和第二线圈彼此磁耦合。 然后，在第一和第二半导体芯片的每一个中，在最上层布线层形成布线和虚拟布线。