公开(公告)号：US20170317669A1

公开(公告)日：2017-11-02

申请号：US15649824

申请日：2017-07-14

Applicant: Renesas Electronics Corporation

Inventor： Shunichi KAERIYAMA

IPC: H03K17/082 ,  H03K17/08

CPC classification number: H03K17/0828 ,  H03K2017/0806

Abstract: The semiconductor device according to one embodiment includes a power transistor and a sense transistor connected in parallel with each other, a first operational amplifier having a non-inverting input terminal connected to an emitter of the sense transistor and an inverting input terminal connected to an emitter of the power transistor, a resistor element having one end connected to the emitter of the sense transistor and another end connected to a first node, and an adjustment transistor placed between the first node and a low-voltage power supply. The first operational amplifier adjusts a current flowing through the adjustment transistor so that an emitter voltage of the power transistor and an emitter voltage of the sense transistor are substantially the same.

公开(公告)号：US20170300329A1

公开(公告)日：2017-10-19

申请号：US15513544

申请日：2014-11-11

Applicant: Renesas Electronics Corporation

Inventor： Koichiro NOGUCHI ,  Osamu OKAZAKI ,  Shunichi KAERIYAMA ,  Koichi NOSE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30076 ,  G06F9/30087 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/52

Abstract: An instruction execution control system includes a plurality of instruction storage units configured to output instructions in an FIFO order to a plurality of instruction execution units configured to execute the instructions; an instruction control unit configured to assign each of a plurality of the sequentially input instructions to one of the instruction storage units, and an output control unit configured to control the output of the instructions from the instruction storage units. When the input instruction is a dummy instruction to be inserted between instructions that should be executed in an execution order, the instruction control unit distributes the input instruction to the plurality of instruction storage units. The output control unit stops the output of the instructions from the instruction storage unit, the instruction output therefrom has become the dummy instruction, to the instruction execution unit until instructions output from all instruction storage units become the dummy instructions.

公开(公告)号：US20160132040A1

公开(公告)日：2016-05-12

申请号：US14886025

申请日：2015-10-17

Applicant: Renesas Electronics Corporation

Inventor： Koichiro NOGUCHI ,  Osamu OKAZAKI ,  Shunichi KAERIYAMA

IPC: G05B19/4099

CPC classification number: G05B19/41805 ,  G05B2219/31066 ,  Y02P90/04

Abstract: A connection relation detecting system according to the present invention includes a plurality of modules which include a plurality of connection ports which can connect with another module, and an information processing device which, when the plurality of modules are connected with each other, is connected to one of the plurality of modules through the connection ports. Each of the plurality of modules includes a connection changing unit which connects the connection ports inside the module in response to a connection change request from the information processing device. The information processing device includes a connection detecting unit which, when the information processing device makes the connection change request to the module, detects a module newly recognized through the module as a module connected to the module to which the connection change request is made.

Abstract translation: 根据本发明的连接关系检测系统包括多个模块，其包括可与另一模块连接的多个连接端口，以及信息处理装置，当多个模块彼此连接时，连接到 多个模块之一通过连接端口。 多个模块中的每一个包括连接改变单元，该连接改变单元响应于来自信息处理设备的连接改变请求而连接模块内部的连接端口。 信息处理装置包括连接检测单元，当信息处理装置向模块进行连接改变请求时，将通过模块新认可的模块检测为连接到进行了连接改变请求的模块的模块。

公开(公告)号：US20160111357A1

公开(公告)日：2016-04-21

申请号：US14982155

申请日：2015-12-29

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Kenji NISHIKAWA ,  Masato KANNO ,  Mika YONEZAWA ,  Shunichi KAERIYAMA ,  Toshinori KIYOHARA

IPC: H01L23/495 ,  H01L49/02

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49551 ,  H01L23/5227 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L28/10 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/29034 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32135 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48249 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/743 ,  H01L2224/75745 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

公开(公告)号：US20160087626A1

公开(公告)日：2016-03-24

申请号：US14856633

申请日：2015-09-17

Applicant: Renesas Electronics Corporation

Inventor： Shunichi KAERIYAMA

IPC: H03K17/687 ,  G01R19/00

CPC classification number: H02M7/5387 ,  G01R19/0092 ,  H02M1/084 ,  H02M2001/0009 ,  H03K17/687

Abstract: A power control circuit according to one embodiment includes an H-bridge circuit formed using a plurality of power transistors. The power transistors are respectively connected to current measurement circuits that measure currents flowing through the power transistors. Each of the power transistors includes a main emitter and a sense emitter through which a current corresponding to a current flowing through the main emitter flows. Each of the current measurement circuits measures a current flowing through each of the power transistors by using a current flowing through the sense emitter included in the power transistor. A control circuit controls the power transistors based on current values respectively measured by the current measurement circuits.

Abstract translation: 根据一个实施例的功率控制电路包括使用多个功率晶体管形成的H桥电路。 功率晶体管分别连接到测量流过功率晶体管的电流的电流测量电路。 每个功率晶体管包括主发射极和感测发射极，与主发射极流过的电流相对应的电流通过该发射极流过。 每个电流测量电路通过使用流过功率晶体管中包括的感测发射极的电流来测量流过每个功率晶体管的电流。 控制电路基于由电流测量电路分别测量的电流值来控制功率晶体管。

公开(公告)号：US20140325322A1

公开(公告)日：2014-10-30

申请号：US14330797

申请日：2014-07-14

Applicant: Renesas Electronics Corporation

Inventor： Shunichi KAERIYAMA

IPC: G06F11/08

CPC classification number: G06F11/08 ,  G01R31/265 ,  G01R31/302 ,  G06K19/0723 ,  H01L23/5227 ,  H01L25/16 ,  H01L25/162 ,  H01L25/167 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H03F3/085 ,  H03F3/189 ,  H03F3/24 ,  H03F3/45475 ,  H03F3/45479 ,  H03F2203/45544 ,  H03F2203/45621 ,  H03K17/0828 ,  H03K17/567 ,  H03K17/689 ,  H03K17/691 ,  H03K17/78 ,  H03K2017/0806 ,  H04B5/0012 ,  H04B5/0075 ,  H04B5/0081 ,  H04L25/0266 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor integrated circuit includes a first transmission circuit generating and outputting a first transmission signal reflecting a first data signal supplied from outside, a first reception circuit reproducing the first data signal based on a first reception signal, a first isolation element isolating the first transmission circuit from the first reception circuit and transmitting the first transmission signal as the first reception signal, a second transmission circuit generating and outputting a second transmission signal reflecting a second data signal supplied from outside, a second reception circuit reproducing the second data signal based on a second reception signal, a second isolation element isolating the second transmission circuit from the second reception circuit and transmitting the second transmission signal as the second reception signal, and a third transmission circuit generating and outputting a third transmission signal reflecting the second data signal.

Abstract translation: 半导体集成电路包括：第一发送电路，生成并输出反映从外部提供的第一数据信号的第一发送信号，第一接收电路，基于第一接收信号再现第一数据信号;第一隔离元件，隔离第一发送电路 从第一接收电路发送第一发送信号作为第一接收信号，生成并输出反映从外部提供的第二数据信号的第二发送信号的第二发送电路，基于第二接收电路再生第二数据信号的第二接收电路 接收信号，第二隔离元件，将第二发送电路与第二接收电路隔离，并发送第二发送信号作为第二接收信号;第三发送电路，生成并输出反映第二数据信号的第三发送信号。