中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

120 records (took 0.017 seconds)

    Semiconductor device
    21.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08810042B2

    公开(公告)日：2014-08-19

    申请号：US13667955

    申请日：2012-11-02

    Applicant: Renesas Electronics Corporation

    Inventor： Yasutaka Nakashiba

    IPC: H01L23/48

    CPC classification number: H01L23/5227 ,  H01L23/48 ,  H01L23/538 ,  H01L23/645 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor and a second spiral inductor formed in the multilayer interconnect, and an interconnect substrate formed over the semiconductor chip and having a third spiral inductor and a fourth spiral inductor. The third spiral inductor overlaps the first spiral inductor in a plan view. The fourth spiral inductor overlaps the second spiral inductor in the plan view. The third spiral inductor and the fourth spiral inductor collectively include a line, the line being spirally wound in a same direction in the third spiral inductor and the fourth spiral inductor.

    Abstract translation: 半导体器件包括具有多层互连的半导体芯片，形成在多层互连中的第一螺旋电感器和第二螺旋电感器，以及形成在半导体芯片上并具有第三螺旋电感器和第四螺旋电感器的互连衬底。 第三螺旋电感器在平面图中与第一螺旋电感器重叠。 第四螺旋电感器在平面图中与第二螺旋电感器重叠。 第三螺旋电感器和第四螺旋电感器共同地包括线，该线在第三螺旋电感器和第四螺旋电感器中以相同的方向螺旋缠绕。

    Semiconductor device having high-frequency interconnect
    22.
    发明授权
    Semiconductor device having high-frequency interconnect 有权
    具有高频互连的半导体器件

    公开(公告)号：US08779595B2

    公开(公告)日：2014-07-15

    申请号：US13871448

    申请日：2013-04-26

    Applicant: Renesas Electronics Corporation

    Inventor： Yasutaka Nakashiba

    IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L29/00

    CPC classification number: H01L23/535 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/585 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in plan view. The semiconductor device further includes dummy conductor patterns (first dummy conductor patterns) in the interconnect layer in which the high-frequency interconnect is disposed.

    Abstract translation: 提供了包括高频互连和虚设导体图案（第二虚拟导体图案）的半导体器件。 虚设导体图案设置在与布置高频互连的互连层不同的互连层中。 虚设导体图案设置成在平面图中远离与高频互连重叠的区域。 半导体器件还包括配置有高频互连的互连层中的虚设导体图案（第一虚设导体图案）。

    Semiconductor device
    23.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08525295B2

    公开(公告)日：2013-09-03

    申请号：US13682591

    申请日：2013-01-04

    Applicant: Renesas Electronics Corporation

    Inventor： Yasutaka Nakashiba

    IPC: H01L27/08

    CPC classification number: H01L27/0617 ,  H01L23/5227 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a substrate, a transistor formed over the substrate, insulating layers formed over the substrate, a multilayer wiring formed in the insulating layers, a first inductor formed in the insulating layers, and a second inductor formed over the first inductor and overlapping the first inductor. The insulating layers contain a silicon, wherein at least the two insulating layers are formed between the first inductor and the second inductor, and the first inductor and the second inductor are a spiral wiring pattern.

    Abstract translation: 半导体器件包括衬底，形成在衬底上的晶体管，形成在衬底上的绝缘层，形成在绝缘层中的多层布线，形成在绝缘层中的第一电感器，以及形成在第一电感器上并重叠的第二电感器 第一个电感。 绝缘层包含硅，其中至少两个绝缘层形成在第一电感器和第二电感器之间，第一电感器和第二电感器是螺旋布线图案。

    Semiconductor device
    24.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08513783B2

    公开(公告)日：2013-08-20

    申请号：US13760812

    申请日：2013-02-06

    Applicant: Renesas Electronics Corporation

    Inventor： Yasutaka Nakashiba

    IPC: H01L23/48

    CPC classification number: H01L23/585 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device (1) includes a wiring (10) and dummy conductor patterns (20). The wiring (10) is a wiring through which a current with a frequency of 5 GHz or higher flows. Near the wiring (10), the dummy conductor patterns (20) are formed. A planar shape of each of the dummy conductor patterns (20) is equivalent to a shape with an internal angle larger than 180°.

    Abstract translation: 半导体器件（1）包括布线（10）和虚设导体图案（20）。 布线（10）是流过5GHz以上的电流的布线。 在布线（10）附近，形成虚设导体图案（20）。 每个虚设导体图案（20）的平面形状等同于内角大于180°的形状。

    Semiconductor device
    25.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08461907B2

    公开(公告)日：2013-06-11

    申请号：US13707150

    申请日：2012-12-06

    Applicant: Renesas Electronics Corporation

    Inventor： Hiroaki Ohkubo ,  Yasutaka Nakashiba

    IPC: H01H85/00

    CPC classification number: H01L23/5252 ,  G11C17/143 ,  G11C17/16 ,  G11C29/027 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.

    Abstract translation: 半导体器件包括信号输出单元和判定单元。 信号输出单元包括m（> = 2）个保险丝，NAND门，电阻元件和输出端。 决定单元判定在信号输出单元中包括的m个熔丝中是否断开了n个以上的熔丝（m> = n> = 2），并输出判定结果。 当m = n = 2时，判定单元由具有连接到保险丝的相应端的两个输入端的NOR门构成。 因此，当判定结果为肯定时，在或非门的输出端输出H电平电位信号。 另一方面，当判定结果为负时，在输出端输出L电平电位信号。

    Semiconductor device and method of manufacturing the same
    27.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US11435525B2

    公开(公告)日：2022-09-06

    申请号：US16874176

    申请日：2020-05-14

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

    IPC: G02B6/122 ,  G02B6/30 ,  G02B6/12 ,  G02B6/24 ,  H04B10/67

    Abstract: A semiconductor device includes a first insulating film, a first optical waveguide and a second optical waveguide. The first insulating film has a first surface and a second surface opposite to the first surface. The first optical waveguide is formed on the first surface of the first insulating film. The second optical waveguide is formed on the second surface of the first insulating film. The second optical waveguide, in plan view, overlaps with an end portion of the first optical waveguide without overlapping with another end portion of the first optical waveguide.

    Semiconductor device
    28.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11307479B2

    公开(公告)日：2022-04-19

    申请号：US16829509

    申请日：2020-03-25

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Teruhiro Kuwajima ,  Yasutaka Nakashiba

    IPC: G02F1/025 ,  G02F1/225 ,  G02F1/01 ,  G02F1/21

    Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.

Patent Agency Ranking