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    OPTIMIZING POWER IN A MEMORY DEVICE
    21.
    发明申请
    OPTIMIZING POWER IN A MEMORY DEVICE 有权

    公开(公告)号：US20220350390A1

    公开(公告)日：2022-11-03

    申请号：US17748704

    申请日：2022-05-19

    Applicant: Rambus Inc.

    Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

    IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06

    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

    OPTIMIZING POWER IN A MEMORY DEVICE
    22.
    发明申请
    OPTIMIZING POWER IN A MEMORY DEVICE 有权

    公开(公告)号：US20210041932A1

    公开(公告)日：2021-02-11

    申请号：US16947973

    申请日：2020-08-26

    Applicant: Rambus Inc.

    Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

    IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06

    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

    DATA BUFFER WITH STROBE-BASED PRIMARY INTERFACE AND A STROBE-LESS SECONDARY INTERFACE
    28.
    发明申请
    DATA BUFFER WITH STROBE-BASED PRIMARY INTERFACE AND A STROBE-LESS SECONDARY INTERFACE 有权
    数据缓冲器与基于STROBE的主界面和无障碍二次接口

    公开(公告)号：US20160041781A1

    公开(公告)日：2016-02-11

    申请号：US14820207

    申请日：2015-08-06

    Applicant: RAMBUS INC.

    Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Dinesh Patil ,  Mohammad Hekmat

    IPC: G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/20 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093

    Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

    Abstract translation: 描述了具有基于选通脉冲的主界面和在存储器模块上使用的无频闪次要接口的数据缓冲器。 一个存储器模块包括地址缓冲器，数据缓冲器和多个动态随机存取存储器（DRAM）器件。 地址缓冲器通过无闪光次要接口向数据缓冲器和DRAM器件提供定时参考，用于数据缓冲器和DRAM器件之间的一个或多个事务。

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