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53 条记录 (耗时 0.041 秒)

    COUNTING PARTICLES USING AN ELECTRICAL DIFFERENTIAL COUNTER
    23.
    发明申请
    COUNTING PARTICLES USING AN ELECTRICAL DIFFERENTIAL COUNTER 有权
    使用电气差分计数器计数颗粒

    公开(公告)号：US20130295588A1

    公开(公告)日：2013-11-07

    申请号：US13884580

    申请日：2011-11-09

    申请人： Nicholas Watkins ,  Rashid Bashir ,  William Rodriguez ,  Xuanhong Cheng ,  Mehmet Toner ,  Grace Chen ,  Aaron Oppenheimer

    发明人： Nicholas Watkins ,  Rashid Bashir ,  William Rodriguez ,  Xuanhong Cheng ,  Mehmet Toner ,  Grace Chen ,  Aaron Oppenheimer

    IPC分类号： G01N27/02

    CPC分类号： G01N27/02 ,  B01L2200/0652 ,  B01L2300/0877 ,  C12M41/36 ,  G01N15/12 ,  G01N15/1245 ,  G01N33/56972 ,  G01N2015/1006 ,  G01N2015/1486

    摘要： This disclosure relates to methods and devices to count particles of interest, such as cells. The methods include obtaining a fluid sample that may contain particles of interest; counting all types of particles in a portion of the sample using a first electrical differential counter to generate a first total; removing any particles of interest from the portion of the fluid sample; counting any particles remaining in the portion of the fluid sample using a second electrical differential counter after the particles of interest are removed to generate a second total; and calculating a number of particles of interest originally in the fluid sample by subtracting the second total from the first total, wherein the difference is the number of particles of interest in the sample. These methods and related devices can be used, for example, to produce a robust, inexpensive diagnostic kit for CD4+ T cell counting in whole blood samples.

    摘要翻译： 本公开涉及计算感兴趣的颗粒例如细胞的方法和装置。 所述方法包括获得可含有感兴趣的颗粒的流体样品; 使用第一电差分计数器对样品的一部分中的所有类型的颗粒计数以产生第一总数; 从流体样品的一部分去除任何感兴趣的颗粒; 在除去感兴趣的颗粒之后，使用第二电差速器计数器在流体样品的部分中剩余的任何颗粒计数以产生第二总数; 以及通过从第一个总计中减去第二个总计来计算最初在流体样品中的感兴趣的颗粒数，其中差值是样品中的感兴趣的颗粒数。 这些方法和相关装置可用于例如在全血样品中产生用于CD4 + T细胞计数的稳健且廉价的诊断试剂盒。

    High sensitivity micro-machined pressure sensors and acoustic transducers
    27.
    发明授权
    High sensitivity micro-machined pressure sensors and acoustic transducers 失效
    高灵敏度微加工压力传感器和声学传感器

    公开(公告)号：US6012335A

    公开(公告)日：2000-01-11

    申请号：US932410

    申请日：1997-09-17

    申请人： Rashid Bashir ,  Abul Kabir

    发明人： Rashid Bashir ,  Abul Kabir

    IPC分类号： G01L9/00 ,  H01L21/027 ,  H01L21/306 ,  H04R31/00 ,  G01L9/12

    CPC分类号： B81C1/00158 ,  G01L9/0042 ,  G01L9/0073 ,  H01L21/0273 ,  H01L21/30608 ,  H04R31/003 ,  B81B2201/0257 ,  B81B2201/0264

    摘要： A method of making a pressure sensor or acoustic transducer having high sensitivity and reduced size. A thin sensing diaphragm is produced by growing a single crystal, highly doped silicon layer on a substrate using a chemical vapor deposition process. The diaphragm is incorporated into a pressure sensor or acoustic transducer which detects pressure variations by a change in the capacitance of a capacitor which includes the diaphragm as a movable member. The thin diaphragm produces a highly sensitive device which can be fabricated in a smaller size than sensors or transducers having thicker diaphragms.

    摘要翻译： 制造具有高灵敏度和减小尺寸的压力传感器或声换能器的方法。 通过使用化学气相沉积工艺在衬底上生长单晶，高掺杂硅层来生产薄感测膜。 隔膜结合到压力传感器或声学传感器中，该传感器或声学换能器通过包括作为可动构件的隔膜的电容器的电容的变化来检测压力变化。 薄隔膜产生高灵敏度的装置，其可以制造成比具有较厚隔膜的传感器或换能器更小的尺寸。

    Semiconductor integrated circuit having a lateral bipolar transistor compatible with deep sub-micron CMOS processing
    28.
    发明授权
    Semiconductor integrated circuit having a lateral bipolar transistor compatible with deep sub-micron CMOS processing 失效
    具有与深亚微米CMOS处理兼容的横向双极晶体管的半导体集成电路

    公开(公告)号：US5952706A

    公开(公告)日：1999-09-14

    申请号：US960298

    申请日：1997-10-29

    申请人： Rashid Bashir

    发明人： Rashid Bashir

    IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L27/102 ,  H01L29/00

    CPC分类号： H01L27/0623 ,  H01L21/8249

    摘要： A semiconductor integrated circuit having a lateral bipolar transistor, is fabricated in a manner compatible with sub-micron CMOS processing. A base contact structure is formed over a bipolar active area, in essentially direct contact to a portion of the upper surface of the active region, essentially concurrent to the formation of a gate electrode on a gate dielectric layer in a CMOS active area. Sidewall spacers, adjacent the base contact region, are formed and a base region formed under the base contact structure using an oblique angle implantation. Emitter region and collector contact regions are formed concurrent with CMOS source and drain regions. An optional, oblique angle collector implant can be performed where desired.

    摘要翻译： 具有横向双极晶体管的半导体集成电路以与亚微米CMOS处理兼容的方式制造。 基极接触结构形成在双极有源区上，基本上与有源区的上表面的一部分直接接触，基本上与在CMOS有源区中的栅极电介质层上形成栅电极同时。 形成与基底接触区域相邻的侧壁间隔物，并且使用倾斜角度注入形成在基底接触结构下方的基底区域。 发射极区域和集电极接触区域与CMOS源极和漏极区域同时形成。 可以根据需要进行可选的斜角收集器植入。

    Planarized trench and field oxide isolation scheme
    29.
    发明授权
    Planarized trench and field oxide isolation scheme 失效
    平面化沟槽和场氧化物隔离方案

    公开(公告)号：US5691232A

    公开(公告)日：1997-11-25

    申请号：US563862

    申请日：1995-11-29

    申请人： Rashid Bashir ,  Francois Hebert ,  Datong Chen

    发明人： Rashid Bashir ,  Francois Hebert ,  Datong Chen

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76229 ,  H01L21/76232 ,  Y10S438/97

    摘要： An isolation method for separating active regions in a semiconductor substrate by combining field oxide formation with trench isolation is disclosed. Deep trenches are etched in a silicon substrate. An oxide layer is deposited over the entire substrate such that the oxide layer also fills the trenches that have been etched. Next, a layer of polysilicon is deposited over the wafer and etched back to form polysilicon spacers. These polysilicon spacers are used to align a photoresist mask that is used to etch the oxide overlying the active regions of the substrate, thereby resulting in fully planarized isolation regions with fully walled active regions.

    摘要翻译： 公开了通过将场氧化物形成与沟槽隔离组合来分离半导体衬底中的有源区的隔离方法。 在硅衬底中蚀刻深沟槽。 在整个基板上沉积氧化物层，使得氧化物层也填充已被蚀刻的沟槽。 接下来，将多晶硅层沉积在晶片上并被回蚀以形成多晶硅间隔物。 这些多晶硅间隔物用于对齐用于蚀刻覆盖衬底的有源区域的氧化物的光致抗蚀剂掩模，由此导致完全平坦化的具有完全有壁的活性区域的隔离区域。

    Process for making self-aligned source/drain polysilicon or polysilicide contacts in field effect transistors
    30.
    发明授权
    Process for making self-aligned source/drain polysilicon or polysilicide contacts in field effect transistors 失效
    在场效应晶体管中制造自对准源/漏多晶硅或多晶硅硅接触的工艺

    公开(公告)号：US5397722A

    公开(公告)日：1995-03-14

    申请号：US273534

    申请日：1994-07-11

    申请人： Rashid Bashir ,  Francois Hebert

    发明人： Rashid Bashir ,  Francois Hebert

    IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/417 ,  H01L21/335

    CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/41783 ,  Y10S148/02

    摘要： A process for forming field effect transistors having self-aligned source/drain contact includes: forming an gate overlying a portion of a semiconductor; forming a first sidewall spacer on the gate; forming a source/drain region in the semiconductor; depositing a conductive layer over the semiconductor so that a step is formed in the conductive layer in a region overlying the gate and the first sidewall spacer; forming a second sidewall spacer on the step; forming a protective layer over a portion of the conducting layer not covered by the second sidewall spacer; removing the second sidewall spacer to expose a portion of the conductive layer but leave covered a portion of the conductive layer underlying the protective layer; and removing the exposed portion of the conductive layer to leave a portion of the conductive layer in contact with the source/drain region and electrically isolated from the gate. The portion of the conductive layer left is the self-aligned contact. Typically, the conductive layer is polysilicon but may alternatively be polysilicide or silicide.

    摘要翻译： 用于形成具有自对准源极/漏极接触的场效应晶体管的工艺包括：形成覆盖半导体的一部分的栅极; 在所述栅极上形成第一侧壁间隔物; 在半导体中形成源/漏区; 在所述半导体上沉积导电层，使得在覆盖所述栅极和所述第一侧壁间隔物的区域中的所述导电层中形成台阶; 在所述台阶上形成第二侧壁间隔物; 在未被所述第二侧壁间隔物覆盖的所述导电层的一部分上形成保护层; 去除所述第二侧壁间隔物以暴露所述导电层的一部分，但是将所述导电层的一部分覆盖在所述保护层下面; 以及去除所述导电层的暴露部分以使所述导电层的一部分与所述源极/漏极区域接触并且与所述栅极电隔离。 剩下的导电层的部分是自对准接触。 通常，导电层是多晶硅，但也可以是多硅化物或硅化物。