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公开(公告)号：US08412970B2
公开(公告)日：2013-04-02
申请号：US13329700
申请日：2011-12-19
IPC分类号： G06F1/00
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/0811 , G06F15/80 , G06F2212/283 , G11C7/1072 , G11C7/1075 , Y02D10/16
摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
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22.发明授权Cache coherency sequencing implementation and adaptive LLC access priority control for CMP 失效缓存一致性排序实现和CMP自适应LLC访问优先级控制公开(公告)号：US08407432B2
公开(公告)日：2013-03-26
申请号：US11173917
申请日：2005-06-30
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.
摘要翻译： 公开了一种用于高速缓存一致性排序实现和自适应LLC访问优先级控制的方法和装置。 一个实施例提供了解决多个内部CMP核心，内部窥探和外部窥探之间的最后一级高速缓存访问优先级的机制。 另一实施例提供了用于在多核CMP系统中实现高速缓存一致性的机制。
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23.发明授权Method and apparatus for dynamically controlling power management in a distributed system 失效在分布式系统中动态控制电源管理的方法和装置公开(公告)号：US07644293B2
公开(公告)日：2010-01-05
申请号：US11479438
申请日：2006-06-29
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3209 , Y02D10/13 , Y02D10/14
摘要： According to one embodiment of the invention, an activity detector comprises a resource partitioned into a plurality of chunks, a power controller and an activity detection unit. In communication with the activity detector and the resource, the power controller, based on measured activity by the activity detector, activates an additional chunk of the plurality of chunks and assigned the additional chunk to a specified agent or deactivates at least one chunk of the plurality of chunks.
摘要翻译： 根据本发明的一个实施例，活动检测器包括被划分成多个块的资源，功率控制器和活动检测单元。 在与活动检测器和资源通信的情况下，功率控制器基于活动检测器测量的活动，激活多个块中的附加块并且将附加块分配给指定的代理或者去激活多个块中的至少一个块 的块。
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24.发明申请METHOD, SYSTEM, AND APPARATUS FOR A CORE ACTIVITY DETECTOR TO FACILITATE DYNAMIC POWER MANAGEMENT IN A DISTRIBUTED SYSTEM 有权一种核心活动检测器在分布式系统中动态动态管理的方法，系统和装置公开(公告)号：US20090006871A1
公开(公告)日：2009-01-01
申请号：US11770618
申请日：2007-06-28
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , H04W52/028 , Y02D70/00
摘要： A system and method to provide source controlled dynamic power management. An activity detector in a source determines expected future resource usage. Based on that expected usage, the source generates a power management command and sends that command to a destination. The destination then adjusts the power level of the resource based in the command.
摘要翻译： 一种提供源控制动态电源管理的系统和方法。 源中的活动检测器确定将来的资源使用量。 根据该预期用途，源产生电源管理命令并将该命令发送到目的地。 然后，目标将根据命令调整资源的功率级别。
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公开(公告)号：US07353338B2
公开(公告)日：2008-04-01
申请号：US11302646
申请日：2005-12-14
申请人： Yen-Cheng Liu , Krishnakanth Sistla , George Cai , Ganapati Srinivasa , Geeyarpuram Santhanakrishnan
发明人： Yen-Cheng Liu , Krishnakanth Sistla , George Cai , Ganapati Srinivasa , Geeyarpuram Santhanakrishnan
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F9/5016 , G06F9/544 , G06F2209/504 , G06F2212/271 , Y02D10/22
摘要： Methods and apparatus to manage credits in a computing system with multiple banks of shared cache are described. In one embodiment, a credit request from a processor core is translated into a physical credit that corresponds to one of the multiple banks of shared cache.
摘要翻译： 描述了在具有多个共享缓存组的计算系统中管理信用的方法和装置。 在一个实施例中，来自处理器核心的信用请求被转换成对应于多个共享高速缓冲存储区之一的物理信用。
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公开(公告)号：US20060053257A1
公开(公告)日：2006-03-09
申请号：US11045525
申请日：2005-01-28
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0815
摘要： Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.
摘要翻译： 防止微处理器和/或计算机系统中的请求冲突。 更具体地，本发明的实施例涉及一种管理处理器和/或计算机系统内的请求冲突的技术，其中可以对一组核心或处理器或代理之间共享的特定高速缓存或高速缓存组进行多次访问 。
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27.发明申请公开(公告)号：US20120089850A1
公开(公告)日：2012-04-12
申请号：US13329700
申请日：2011-12-19
IPC分类号： G06F1/26
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/0811 , G06F15/80 , G06F2212/283 , G11C7/1072 , G11C7/1075 , Y02D10/16
摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
摘要翻译： 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件都具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。
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28.发明申请公开(公告)号：US20120079032A1
公开(公告)日：2012-03-29
申请号：US12889802
申请日：2010-09-24
申请人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
发明人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
CPC分类号： H04L67/10 , G06F15/17325
摘要： Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.
摘要翻译： 用于促进独立消息类别的单向排序的方法，装置和系统。 单向消息排序机制有助于在使用消息类的独立路径的互连之间发送的不同消息类别的消息的单向排序。 在一个方面，第二消息类的消息可能不会传递第一消息类的消息。 此外，当顺序地接收到第一类和第二类的消息时，排序机制确保在转发第二类的消息之前将第一类的消息转发到下一跳并在其中接收。
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29.发明授权公开(公告)号：US08117478B2
公开(公告)日：2012-02-14
申请号：US11618477
申请日：2006-12-29
IPC分类号： G06F1/00
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/0811 , G06F15/80 , G06F2212/283 , G11C7/1072 , G11C7/1075 , Y02D10/16
摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
摘要翻译： 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。
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公开(公告)号：US07689778B2
公开(公告)日：2010-03-30
申请号：US11000768
申请日：2004-11-30
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： In various embodiments, hardware, software and firmware or combinations thereof may be used to prevent cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches.
摘要翻译： 在各种实施例中，可以使用硬件，软件和固件或其组合来防止微处理器和/或计算机系统内的高速缓存冲突。 更具体地，本发明的实施例涉及一种防止处理器和/或计算机系统内的高速缓存冲突的技术，其中可以对特定高速缓存或一组高速缓存进行多次访问。
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