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公开(公告)号：US07353338B2
公开(公告)日：2008-04-01
申请号：US11302646
申请日：2005-12-14
申请人： Yen-Cheng Liu , Krishnakanth Sistla , George Cai , Ganapati Srinivasa , Geeyarpuram Santhanakrishnan
发明人： Yen-Cheng Liu , Krishnakanth Sistla , George Cai , Ganapati Srinivasa , Geeyarpuram Santhanakrishnan
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F9/5016 , G06F9/544 , G06F2209/504 , G06F2212/271 , Y02D10/22
摘要： Methods and apparatus to manage credits in a computing system with multiple banks of shared cache are described. In one embodiment, a credit request from a processor core is translated into a physical credit that corresponds to one of the multiple banks of shared cache.
摘要翻译： 描述了在具有多个共享缓存组的计算系统中管理信用的方法和装置。 在一个实施例中，来自处理器核心的信用请求被转换成对应于多个共享高速缓冲存储区之一的物理信用。
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公开(公告)号：US20070136531A1
公开(公告)日：2007-06-14
申请号：US11302646
申请日：2005-12-14
申请人： Yen-Cheng Liu , Krishnakanth Sistla , George Cai , Ganapati Srinivasa , Geeyarpuram Santhanakrishnan
发明人： Yen-Cheng Liu , Krishnakanth Sistla , George Cai , Ganapati Srinivasa , Geeyarpuram Santhanakrishnan
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F9/5016 , G06F9/544 , G06F2209/504 , G06F2212/271 , Y02D10/22
摘要： Methods and apparatus to manage credits in a computing system with multiple banks of shared cache are described. In one embodiment, a credit request from a processor core is translated into a physical credit that corresponds to one of the multiple banks of shared cache.
摘要翻译： 描述了在具有多个共享缓存组的计算系统中管理信用的方法和装置。 在一个实施例中，来自处理器核心的信用请求被转换成对应于多个共享高速缓冲存储区之一的物理信用。
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公开(公告)号：US08412970B2
公开(公告)日：2013-04-02
申请号：US13329700
申请日：2011-12-19
IPC分类号： G06F1/00
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/0811 , G06F15/80 , G06F2212/283 , G11C7/1072 , G11C7/1075 , Y02D10/16
摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
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4.发明申请公开(公告)号：US20120089850A1
公开(公告)日：2012-04-12
申请号：US13329700
申请日：2011-12-19
IPC分类号： G06F1/26
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/0811 , G06F15/80 , G06F2212/283 , G11C7/1072 , G11C7/1075 , Y02D10/16
摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
摘要翻译： 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件都具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。
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公开(公告)号：US08473766B2
公开(公告)日：2013-06-25
申请号：US13609006
申请日：2012-09-10
IPC分类号： G06F1/00
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/0811 , G06F15/80 , G06F2212/283 , G11C7/1072 , G11C7/1075 , Y02D10/16
摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
摘要翻译： 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件都具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。
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公开(公告)号：US20130031400A1
公开(公告)日：2013-01-31
申请号：US13609006
申请日：2012-09-10
IPC分类号： G06F1/28
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/0811 , G06F15/80 , G06F2212/283 , G11C7/1072 , G11C7/1075 , Y02D10/16
摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
摘要翻译： 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件都具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。
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7.发明申请公开(公告)号：US20070094453A1
公开(公告)日：2007-04-26
申请号：US11256536
申请日：2005-10-21
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/383 , G06F12/0862 , G06F2212/502
摘要： A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.
摘要翻译： 提出了对预取器的动态配置的讨论。 例如，计算线程特定的延迟度量，并通过配置和状态寄存器在每个线程的基础上向软件提供动态反馈。 同样，软件可以选择使用来自寄存器的信息来动态地配置预取行为，并允许软件能够查询性能并配置预取器。
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公开(公告)号：US20070150657A1
公开(公告)日：2007-06-28
申请号：US11316560
申请日：2005-12-22
IPC分类号： G06F12/00
CPC分类号： G06F12/0842
摘要： According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.
摘要翻译： 根据本发明的一个实施例，公开了一种用于选择高速缓存中的多个高速缓存路径的第一子集的方法，用于存储被识别为高优先级硬件线程的硬件线程，以用于与高速缓存通信的多线程处理器进行处理; 将高优先级的硬件线程分配给所选择的第一子集; 监视分配给所选择的多个高速缓存路线的第一子集的高优先级硬件线程的高速缓存使用; 以及如果所述高优先级硬件线程的高速缓存使用基于所述监视超过预定的非活动高速缓存使用阈值，则将所分配的高优先级硬件线程重新分配给所述多个高速缓存路径中的任何高速缓存方式。
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9.发明授权Dynamically adjusting power of non-core processor circuitry including buffer circuitry 有权动态调整包括缓冲电路在内的非核心处理器电路的功率公开(公告)号：US08914650B2
公开(公告)日：2014-12-16
申请号：US13247594
申请日：2011-09-28
申请人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
发明人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
CPC分类号： G06F1/324 , G06F13/4022 , Y02D10/126
摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。 该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。 除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。 该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。 描述和要求保护其他实施例。
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公开(公告)号：US20120179878A1
公开(公告)日：2012-07-12
申请号：US13422806
申请日：2012-03-16
IPC分类号： G06F12/08
CPC分类号： G06F15/17337 , G06F12/0817 , G06F12/0831
摘要： In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent and another PtP link coupled between first and second processors of the MCP, where the on-package PtP link operates at a greater bandwidth than the first PtP link. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，使用多个处理器形成的多芯片处理器（MCP）的链路逻辑可以与耦合在MCP和非封装代理之间的第一点对点（PtP）链路以及耦合在第一 和MCP的第二个处理器，其中的封装PtP链路以比第一个PtP链路更大的带宽工作。 描述和要求保护其他实施例。
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