公开(公告)号：US5624871A

公开(公告)日：1997-04-29

申请号：US699222

申请日：1996-08-19

申请人： Yeow M. Teo ,  Kah S. Seah ,  Lap Chan ,  Che-Chia Wei

发明人： Yeow M. Teo ,  Kah S. Seah ,  Lap Chan ,  Che-Chia Wei

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76895 ,  H01L21/76889 ,  Y10S438/934

摘要： A method for producing an interconnect on a semiconductor device has silicon containing conductive surfaces and dielectric surfaces. The process includes forming separate regions of a blanket first refractory metal silicide on the silicon containing conductive surfaces, the first refractory metal silicide being composed of a first refractory metal and silicon from the surfaces, forming a blanket second refractory metal layer over the device, forming a blanket .alpha.-Si layer over the second refractory metal layer, forming a mask over the device to pattern an interconnect between the separate regions, then etching away the unwanted portions of the refractory metal layers and the .alpha.-Si layer, performing a rapid thermal annealing process on the device forming a low resistance refractory metal silicide between the .alpha.-Si layer and the second refractory metal layer, and then etching away the unwanted portions of the refractory metal layers that are not covered by the refractory metal silicide.

摘要翻译： 在半导体器件上制造互连的方法具有含硅的导电表面和电介质表面。 该方法包括在含硅导电表面上形成覆盖的第一难熔金属硅化物的分开的区域，第一难熔金属硅化物由表面上的第一难熔金属和硅组成，在该器件上形成毯状的第二难熔金属层，形成 在第二耐火金属层上方的覆盖的α-Si层，在器件上形成掩模以对分离区域之间的互连进行图案化，然后蚀刻掉难熔金属层和α-Si层的不需要的部分，执行快速热 在α-Si层和第二难熔金属层之间形成低电阻难熔金属硅化物的器件上的退火工艺，然后蚀刻除了难熔金属硅化物不被覆盖的难熔金属层的不希望的部分。

公开(公告)号：US5346860A

公开(公告)日：1994-09-13

申请号：US088197

申请日：1993-07-06

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/283

CPC分类号： H01L21/76889 ,  H01L21/76895

摘要： A method for fabricating an interconnect structure in an integrated circuit. A first conductive layer is formed over an underlying region in the integrated circuit. The underlying region may be, for example, a semiconductor substrate or a gate electrode. A buffer layer is then formed over the first conductive layer, followed by the formation of an insulating layer over the buffer layer. The insulating layer and the buffer layer are patterned to define a form for the interconnect structure. A second conductive layer is then formed over the integrated circuit, and portions of the first conductive layer, the second conductive layer, and the buffer layer are silicided to form the interconnect structure.

摘要翻译： 一种用于在集成电路中制造互连结构的方法。 在集成电路中的下部区域上形成第一导电层。 下面的区域可以是例如半导体衬底或栅电极。 然后在第一导电层上形成缓冲层，随后在缓冲层上形成绝缘层。 将绝缘层和缓冲层图案化以限定互连结构的形式。 然后在集成电路上形成第二导电层，并且将第一导电层，第二导电层和缓冲层的部分硅化以形成互连结构。

公开(公告)号：US5043778A

公开(公告)日：1991-08-27

申请号：US238978

申请日：1988-08-25

申请人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

发明人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

IPC分类号： H01L21/285 ,  H01L21/308 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/66636 ,  H01L21/28525 ,  H01L21/3086 ,  H01L21/76218 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L27/0921 ,  H01L27/0928 ,  Y10S257/90

摘要： A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusioins 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

摘要翻译： 具有源极/漏极 - 接触区域36的MOS体器件，其几乎完全由电介质35隔离。这些通过使用硅蚀刻形成凹槽形成的“源极/漏极”区域36，用氧化物限制蚀刻的凹槽，并且填充 与多晶硅。 短的各向同性氧化物蚀刻，随后是多晶硅长丝沉积，然后在氧化物隔离的源极/漏极 - 接触区域36和有源器件的沟道区域33之间接触。 通过该接触的小面积的扩散将在硅中形成小的漫射体44，其作为电学有效的源极/漏极区域。 在栅极上使用侧壁氮化物细丝30允许硅蚀刻步骤自对准。

公开(公告)号：US4920073A

公开(公告)日：1990-04-24

申请号：US350429

申请日：1989-05-11

申请人： Che-Chia Wei ,  Thomas E. Tang ,  James G. Bohlman ,  Monte A. Douglas

发明人： Che-Chia Wei ,  Thomas E. Tang ,  James G. Bohlman ,  Monte A. Douglas

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L23/52

CPC分类号： H01L29/665 ,  H01L21/3211 ,  Y10S148/113 ,  Y10S148/147

摘要： The present invention provides a method for inhibiting the oxidation of a titanium layer during the direct reaction of the titanium with exposed silicon areas of an integrated circuit. In one embodiment of the present invention, a titanium nitride layer is formed on the surface of the titanium layer in the reactor where the titanium layer is deposited. The titanium nitride layer provides an effective barrier against oxidation. Thus, the formation of titanium dioxide is inhibited. In addition, in those areas where titanium nitride local interconnect is to be formed between diffused areas, the extra thickness provided by the top titanium nitride layer adds in the integrity of the conductive layers. By conducting the silicidation in a nitride atmosphere, diffusion of the nitride from the titanium nitride layer into the titanium layer and substitution of those lost nitrogen atoms by the atmosphere occurs thus providing a blocking layer for the formation of titanium silicide shorts.

摘要翻译： 本发明提供了在钛与集成电路的暴露的硅区域的直接反应期间抑制钛层的氧化的方法。 在本发明的一个实施例中，在沉积钛层的反应器中的钛层的表面上形成氮化钛层。 氮化钛层提供了抗氧化的有效屏障。 因此，二氧化钛的形成被抑制。 此外，在要在扩散区域之间形成氮化钛局部互连的区域中，由顶部氮化钛层提供的额外的厚度增加了导电层的完整性。 通过在氮化物气氛中进行硅化，氮化物从钛氮化物层扩散到钛层中，并且由于大气中的那些失去的氮原子而被发生，从而提供用于形成硅化钛短路的阻挡层。

公开(公告)号：US5837587A

公开(公告)日：1998-11-17

申请号：US726335

申请日：1996-10-03

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/66492 ,  H01L21/823814 ,  H01L29/6659

摘要： A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

公开(公告)号：US5434448A

公开(公告)日：1995-07-18

申请号：US307476

申请日：1994-09-16

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/82 ,  H01L23/525 ,  H01L29/41 ,  H01L27/02 ,  H01L29/04

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S257/915

摘要： A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.

摘要翻译： 提供了可编程半导体接触结构和方法。 半导体衬底具有用于形成互连的第一图案化导电层。 第一绝缘层覆盖在第一图案化导电层上。 通过绝缘层形成开口到第一图案化导电层以形成接触通孔。 缓冲层覆盖第一绝缘层的部分并覆盖开口。 第二导电层覆盖缓冲层。 然后第三导电层覆盖集成电路。 缓冲层是诸如非晶硅的材料，其用作抗熔丝并且可以通过应用相对高的编程电压进行编程。

公开(公告)号：US5166770A

公开(公告)日：1992-11-24

申请号：US38394

申请日：1987-04-15

申请人： Thomas E. Tang ,  Che-Chia Wei ,  Cheng-Eng D. Chen

发明人： Thomas E. Tang ,  Che-Chia Wei ,  Cheng-Eng D. Chen

IPC分类号： H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/285 ,  H01L23/53257 ,  H01L27/0928 ,  H01L2924/0002

摘要： Preferred embodiments include silicon complementary MOSFETs with titanium silicided junctions (38, 58) and direct contacts of aluminum metallization (61, 62) to the p junctions (58) which avoids the high contact resistance of the silicide (60) to p silicon (58). Preferred embodiments also include silicided polysilicon lines without corresponding silicided MOSFET junctions.

摘要翻译： 优选实施例包括具有钛硅化物结（38,58）的硅互补MOSFET和铝金属化（61,62）与p结（58）的直接接触，避免了硅化物（60）对p硅（58）的高接触电阻 ）。 优选实施例还包括没有相应的硅化MOSFET结的硅化多晶硅线。

公开(公告)号：US5124280A

公开(公告)日：1992-06-23

申请号：US648554

申请日：1991-01-31

申请人： Che-Chia Wei ,  Fu-Tai Liou

发明人： Che-Chia Wei ,  Fu-Tai Liou

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53271 ,  H01L21/76889 ,  H01L21/76895 ,  H01L2924/0002

摘要： Local interconnect is defined in a polycrystalline silicon layer. Openings to underlying conducting regions are made through an insulating layer after the local interconnect conductor definition. A thin extra polycrystalline silicon layer is then deposited over the device and etched back to form polycrystalline silicon sidewall elements. These sidewalls connect the polycrystalline silicon local interconnect conductors to the underlying conductive regions. Standard silicidation techniques are then used to form a refractory metal silicide on the exposed underlying conductive regions, the polycrystalline silicon sidewall elements, and the polycrystalline silicon local interconnect conductors. This results in a complete silicided connection between features connected by the local interconnect conductors.

公开(公告)号：US4690730A

公开(公告)日：1987-09-01

申请号：US876947

申请日：1986-06-20

申请人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway ,  David A. Bell

发明人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway ,  David A. Bell

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52 ,  H01L29/78 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/76895 ,  H01L2924/0002

摘要： A cap oxide (or oxide/nitride) prevents silicon outdiffusion during the reaction step which forms direct-react titanium silicide.

摘要翻译： 氧化物（或氧化物/氮化物）在反应步骤期间防止硅扩散，其形成直接反应的硅化钛。

公开(公告)号：US4676866A

公开(公告)日：1987-06-30

申请号：US837482

申请日：1986-03-07

申请人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway

发明人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/11 ,  C23F1/02 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L27/11526 ,  H01L21/32053 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11543

摘要： A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. A second titanium layer is then deposited overall and again reacted, to thicken the nitride layer without increasing the thickness of the silicide layers. This conductive layer is patterned and etched to provide local interconnects with a sheet resistance of the order to ten ohms per square, and also etch stops. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect capability fulfills all of the functions which a buried contact capability fulfill, and fulfills other functions as well.

摘要翻译： 用于VLSI集成电路的局部互连系统。 在氮气气氛中暴露的山沟和栅极区域的自对准硅化过程中，整体形成导电氮化钛层。 然后将第二钛层整体沉积并再次反应，以增加氮化物层而不增加硅化物层的厚度。 对该导电层进行图案化和蚀刻，以提供局部互连，其平面电阻为10欧姆/平方，并且也蚀刻停止。 此外，这种局部互连级别允许接触与护城河边界不对准，因为氮化钛局部互连层可以从护壕向上叠加到场氧化物上，以提供用于接触孔的底部接触和扩散屏障 通过层间氧化物蚀刻。 这种局部互连功能可以满足埋入式接触能力的所有功能，并满足其他功能。