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80 条记录 (耗时 0.026 秒)

    Semiconductor memory
    23.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US07206242B2

    公开(公告)日：2007-04-17

    申请号：US11013688

    申请日：2004-12-17

    申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1051 ,  G11C2207/107

    摘要： A semiconductor memory includes a converter configured to convert each read-data of plural bits read from a memory core into serial data, respectively, in synchronization with a read clock to generate converted read-data. An output register holds the converted read-data in synchronization with the read clock. A selector selects one bit from each plural bits of the converted read-data, in accordance with a control data, and to supply the selected bit to the output register.

    摘要翻译： 半导体存储器包括：转换器，被配置为与读取时钟同步地分别将从存储器芯读取的多个位的每个读取数据转换为串行数据，以产生转换的读取数据。 输出寄存器与读取时钟同步地保存转换的读取数据。 选择器根据控制数据从转换的读取数据的每个多个比特中选择一个比特，并将所选择的比特提供给输出寄存器。

    MOS-type semiconductor integrated circuit
    24.
    发明授权
    MOS-type semiconductor integrated circuit 失效

    公开(公告)号：US06700411B2

    公开(公告)日：2004-03-02

    申请号：US10234106

    申请日：2002-09-05

    申请人： Katsuki Matsudera ,  Masaru Koyanagi

    发明人： Katsuki Matsudera ,  Masaru Koyanagi

    IPC分类号： H03K19094

    CPC分类号： H03K19/0963 ,  H03K19/00315

    摘要： An MOS-type semiconductor integrated circuit has two MOS transistors of the opposite conductivity channel types connected in series between a high-voltage potential terminal and a ground potential terminal. Those two MOS transistors constitute an inverter and their gates are connected together to an input node. As output nodes, first and second nodes are provided with a current path in between which includes transistors whose gates are connected to the high-voltage potential terminal. A current path including the first transistor which constitutes a switch is inserted between the first node and the output node, and a current path including the second transistor and a barrier transistor is inserted between the second node and the output node. The gates of the first and second transistors are respectively connected with complementary clock signals. The bate of the barrier transistor is connected to the high-voltage potential terminal.

    Semiconductor integrated circuit having output buffer
    25.
    发明授权
    Semiconductor integrated circuit having output buffer 失效

    公开(公告)号：US06563351B2

    公开(公告)日：2003-05-13

    申请号：US09965951

    申请日：2001-09-27

    申请人： Tadashi Onizawa ,  Natsuki Kushiyama ,  Masaru Koyanagi ,  Katsuki Matsudera

    发明人： Tadashi Onizawa ,  Natsuki Kushiyama ,  Masaru Koyanagi ,  Katsuki Matsudera

    IPC分类号： H03B100

    CPC分类号： H03K19/01707 ,  H03K17/102 ,  H03K17/162

    摘要： A semiconductor integrated circuit includes first and second MOS transistors and a capacitor. The first MOS transistor has a drain connected to an output terminal, a gate and a source. The second MOS transistor has a gate, a drain connected to the source of the first MOS transistor and a source and has the same conductivity type as the first MOS transistor. The capacitor has one electrode connected to the gate of the first MOS transistor and the other electrode connected to a node whose potential changes in a complementary fashion with respect to the drain potential of the first MOS transistor and functions to cancel out an influence, caused by the coupling of a mirror capacitor which exists between the gate and drain of the first MOS transistor, affecting the gate potential of the first MOS transistor.

    Semiconductor memory device
    27.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06272063B1

    公开(公告)日：2001-08-07

    申请号：US09535952

    申请日：2000-03-27

    申请人： Kenichi Matoba ,  Masaru Koyanagi

    发明人： Kenichi Matoba ,  Masaru Koyanagi

    IPC分类号： G11C800

    CPC分类号： G11C8/12

    摘要： A semiconductor memory device comprises a first core section including a plurality of memory cell arrays, a second core section including a plurality of memory cell arrays and provided below the first core section, a third core section including a plurality of memory cell arrays and provided in a right side of the first core section, and a fourth core section including a plurality of memory cell arrays and provided in a right side of the second core section, wherein at least a part of the memory cell arrays of the first core section and at least a part of the memory cell arrays of the fourth core section are simultaneously activated, and at least a part of the memory cell arrays of the second core section and at least a part of the memory cell arrays of the third core section are simultaneously activated.

    摘要翻译： 半导体存储器件包括：第一芯部分，包括多个存储单元阵列;第二芯部分，包括多个存储单元阵列并且设置在第一芯部下;第三核心部分，包括多个存储单元阵列， 第一芯部的右侧，以及包括多个存储单元阵列并设置在第二芯部的右侧的第四芯部，其中，第一芯部的存储单元阵列的至少一部分和 同时激活第四核心部分的存储单元阵列的至少一部分，并且第二核心部分的至少一部分存储单元阵列和第三核心部分的至少一部分存储单元阵列同时被激活 。

    Substrate bias circuit
    29.
    发明授权
    Substrate bias circuit 失效
    基板偏置电路

    公开(公告)号：US5202588A

    公开(公告)日：1993-04-13

    申请号：US827267

    申请日：1992-01-29

    申请人： Ryosuke Matsuo ,  Masaru Koyanagi

    发明人： Ryosuke Matsuo ,  Masaru Koyanagi

    IPC分类号： G11C11/413 ,  G05F3/20 ,  G11C11/408 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07 ,  H03K19/094

    CPC分类号： G05F3/205 ,  H02M3/07

    摘要： There is disclosed a substrate bias circuit including an oscillation circuit oscillating at a predetermined frequency; a control signal generation circuit operative to generate a control signal for changing, on the basis of an output from the oscillation circuit, a substrate potential in a direction to ensure a threshold level of a transistor so that it becomes greater; and a charge pump circuit including a capacitor and operative to control discharge of the capacitor by said control signal to thereby change the substrate potential.

    摘要翻译： 公开了一种衬底偏置电路，包括以预定频率振荡的振荡电路; 控制信号生成电路，用于产生控制信号，用于根据来自振荡电路的输出，在确保晶体管的阈值电平使其变大的方向上改变衬底电位; 以及电荷泵电路，其包括电容器，并且用于通过所述控制信号控制电容器的放电，从而改变衬底电位。