公开(公告)号：US09281389B2

公开(公告)日：2016-03-08

申请号：US13758917

申请日：2013-02-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon Park ,  In Hyuk Song ,  Dong Soo Seo ,  Kwang Soo Kim ,  Kee Ju Um

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/0634 ,  H01L29/2003

Abstract: Disclosed herein is a semiconductor device including: a source electrode formed on one side of an N-type AlGaN layer; N-type and P-type AlGaN layers formed on the other side of the P-type AlGaN layer and formed in a direction perpendicular to the source electrode; a gate electrode formed on one side of the N-type and P-type AlGaN layers; and a drain electrode formed on the other side of the N-type and P-type AlGaN layers.

Abstract translation: 本发明公开了一种半导体器件，包括：形成在N型AlGaN层一侧的源电极; 在P型AlGaN层的另一侧形成并且沿垂直于源电极的方向形成的N型和P型AlGaN层; 形成在N型和P型AlGaN层一侧的栅电极; 以及形成在N型和P型AlGaN层的另一侧的漏电极。

公开(公告)号：US09245986B2

公开(公告)日：2016-01-26

申请号：US14322346

申请日：2014-07-02

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Jae Hoon Park ,  Dong Soo Seo ,  Chang Su Jang

IPC: H01L29/78 ,  H01L29/00 ,  H01L21/336 ,  H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L29/36

CPC classification number: H01L29/7397 ,  H01L21/265 ,  H01L21/26513 ,  H01L29/36 ,  H01L29/66348

Abstract: A power semiconductor device may include: a base substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.

Abstract translation: 功率半导体器件可以包括：基底衬底，其包括第一导电型漂移层; 设置在所述基底基板的另一个表面上的第二导电型半导体基板; 第一导电型扩散层，设置在所述基底衬底中，其杂质浓度高于所述漂移层的杂质浓度; 设置在所述基底基板的一个表面内的第二导电型阱层; 从包括所述阱层的所述基底基板的一个表面形成的沟槽，以在深度方向上穿过所述扩散层; 设置在所述基底基板的表面上的第一绝缘膜; 以及设置在沟槽中的第一电极。 扩散层在横向上的杂质掺杂浓度的峰值点可以位于与沟槽的侧表面接触的区域中。

公开(公告)号：US20150060999A1

公开(公告)日：2015-03-05

申请号：US14451030

申请日：2014-08-04

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Dong Soo SEO ,  Jae Hoon Park ,  In Hyuk Song ,  Ji Yeon Oh ,  Kee Ju Um

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/0878 ,  H01L29/42376 ,  H01L29/435 ,  H01L29/4983 ,  H01L29/7813

Abstract: A power semiconductor device may include: a drift layer having a first conductivity; a hole accumulating layer formed on the drift layer and having the first conductivity; a well layer formed on the hole accumulating layer and having a second conductivity; an emitter region formed in an internal portion of an upper portion of the well layer and having the first conductivity; and trench gates penetrating through the emitter region, the well layer, and the hole accumulating layer, and having a gate insulating layer formed on a surface thereof. The trench gate may be sequentially divided into a first gate part, a second gate part, and a third gate part from an upper portion thereof depending on a height of a material filled in the trench gate, the first to third gate parts having different resistances from each other.

Abstract translation: 功率半导体器件可以包括：具有第一导电性的漂移层; 形成在漂移层上并具有第一导电性的孔积聚层; 形成在所述蓄积层上并具有第二导电性的阱层; 发射极区，形成在所述阱层的上部的内部，并具有第一导电性; 以及穿过发射极区域，阱层和空穴积聚层的沟槽栅极，并且在其表面上形成栅极绝缘层。 沟槽栅极可以根据填充在沟槽栅极中的材料的高度从其上部依次分为第一栅极部分，第二栅极部分和第三栅极部分，第一至第三栅极部分具有不同的电阻 从彼此。

公开(公告)号：US20140159106A1

公开(公告)日：2014-06-12

申请号：US13874038

申请日：2013-04-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju UM ,  Dong Soo Seo ,  Chang Su Jang ,  In Hyuk Song ,  Jaehoon Park

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/423 ,  H01L29/66333

Abstract: There is provided a power semiconductor device, including: a first conductive type drift layer, a second conductive type termination layer formed on an upper portion of an edge of the drift layer, and a high concentration first conductive type channel stop layer formed on a side surface of the edge of the drift layer.

Abstract translation: 提供了一种功率半导体器件，包括：第一导电型漂移层，形成在漂移层的边缘的上部上的第二导电型端接层和形成在侧面的高浓度第一导电型沟道阻挡层 漂移层边缘的表面。

公开(公告)号：US20140117373A1

公开(公告)日：2014-05-01

申请号：US13758917

申请日：2013-02-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon Park ,  In Hyuk Song ,  Dong Soo Seo ,  Kwang Soo Kim ,  Kee Ju Um

IPC: H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/0634 ,  H01L29/2003

Abstract: Disclosed herein is a semiconductor device including: a source electrode formed on one side of an N-type AlGaN layer; N-type and P-type AlGaN layers formed on the other side of the P-type AlGaN layer and formed in a direction perpendicular to the source electrode; a gate electrode formed on one side of the N-type and P-type AlGaN layers; and a drain electrode formed on the other side of the N-type and P-type AlGaN layers.

Abstract translation: 本发明公开了一种半导体器件，包括：形成在N型AlGaN层一侧的源电极; 在P型AlGaN层的另一侧形成并且沿垂直于源电极的方向形成的N型和P型AlGaN层; 形成在N型和P型AlGaN层一侧的栅电极; 以及形成在N型和P型AlGaN层的另一侧的漏电极。

公开(公告)号：US08653628B1

公开(公告)日：2014-02-18

申请号：US13688320

申请日：2012-11-29

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： In Hyuk Song ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/00

CPC classification number: H01L29/6634 ,  H01L21/046 ,  H01L21/22 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66674 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7825

Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.

Abstract translation: 本发明公开了一种功率半导体器件，包括：具有一个表面和另一个表面并由第一导电型漂移层形成的基底基板; 形成在所述基底基板的一个表面上并且具有比所述第一导电型漂移层的浓度高的浓度的第一导电型扩散层; 以及形成为从厚度方向包括第二导电类型阱层的基底基板的一个表面穿过第二导电类型阱层和第一导电型扩散层的沟槽。

公开(公告)号：US20140015003A1

公开(公告)日：2014-01-16

申请号：US13761127

申请日：2013-02-06

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Soo Koo ,  Bum Seok Suh ,  In Hyuk Song ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397

Abstract: Disclosed herein are a semiconductor device, and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate, a base region formed on an upper region of an inside of the semiconductor substrate, at least one gate electrode that penetrates through the base region and has an inverted triangular shape, a gate insulating film formed to enclose an upper portion of the semiconductor substrate and the gate electrode, an inter-layer insulating film formed on an upper portion of the gate electrode and the gate insulating film, an emitter region formed inside the base region and on both sides of the gate electrode, an emitter metal layer formed on an upper portion of the base region and inter-layer insulating film, and a buffer region formed to enclose a lower portion of the gate electrode and to be spaced apart from the base region.

Abstract translation: 本发明公开了一种半导体器件及其制造方法。 半导体器件包括半导体衬底，形成在半导体衬底的内部的上部区域中的基极区域，穿过基极区域并具有倒三角形形状的至少一个栅极电极，形成为封闭 半导体衬底的上部和栅电极，形成在栅极电极和栅极绝缘膜的上部的层间绝缘膜，形成在基极区域内和栅电极两侧的发射极区域， 形成在基极区域的上部的发射极金属层和层间绝缘膜，以及形成为包围栅电极的下部并与基极间隔开的缓冲区域。

公开(公告)号：US09627470B2

公开(公告)日：2017-04-18

申请号：US14301328

申请日：2014-06-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Jae Hoon Park ,  Kee Ju Um ,  Dong Soo Seo

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L29/0611 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802

Abstract: There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the nth layer is Pn, P1

公开(公告)号：US09502498B2

公开(公告)日：2016-11-22

申请号：US14617158

申请日：2015-02-09

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kyu Hyun Mo ,  Dong Soo Seo ,  Chang Su Jang ,  Jae Hoon Park ,  In Hyuk Song

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

Abstract: A power semiconductor device may include a first conductivity type semiconductor substrate, a super-junction portion disposed on the first conductivity type semiconductor substrate and including a first conductivity type pillar and a second conductivity type pillar arranged in an alternating manner, and a three-dimensional (3D) gate portion disposed on the first conductivity type pillar. The 3D gate portion is disposed on the first conductivity type pillar to reduce the widths of the first and second conductivity type pillars, thereby effectively reducing a device size.

Abstract translation: 功率半导体器件可以包括第一导电类型半导体衬底，设置在第一导电类型半导体衬底上的超接合部分，并且包括交替排列的第一导电型柱和第二导电型柱，并且三维 （3D）门部分，设置在第一导电型柱上。 3D栅极部分设置在第一导电型柱上以减小第一和第二导电型柱的宽度，从而有效地减小了器件尺寸。

公开(公告)号：US09287363B2

公开(公告)日：2016-03-15

申请号：US14273269

申请日：2014-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon Park ,  In Hyuk Song ,  Chang Su Jang ,  Kee Ju Um

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/1608 ,  H01L21/049 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device may include: preparing a substrate formed of SiC; depositing crystalline or amorphous silicon (Si) on one surface of the substrate to form a first semiconductor layer; and performing a heat treatment under a nitrogen atmosphere to form a second semiconductor layer formed of SiCN between the substrate and the first semiconductor layer.

Abstract translation: 制造半导体器件的方法可以包括：制备由SiC形成的衬底; 在所述衬底的一个表面上沉积晶体或非晶硅（Si）以形成第一半导体层; 并在氮气气氛下进行热处理，以在衬底和第一半导体层之间形成由SiCN形成的第二半导体层。