公开(公告)号：US20150187921A1

公开(公告)日：2015-07-02

申请号：US14273159

申请日：2014-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon PARK ,  In Hyuk SONG ,  Dong Soo SEO ,  Ji Yeon OH ,  Kee Ju UM

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1025 ,  H01L29/1095 ,  H01L29/267 ,  H01L29/7802 ,  H01L29/7813

Abstract: A power semiconductor device may include a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed in an upper portion of the first semiconductor region; a third semiconductor region having a first conductivity type and formed in an upper portion of the second semiconductor region; and a trench gate formed by penetrating from the third semiconductor region to the first semiconductor region. A portion of at least one of the first semiconductor region, the second semiconductor region, and the third semiconductor region may include a device protection material of which a conduction band has a main state and a satellite state in an E-k diagram, and a curvature of the device protection material in the satellite state may be lower than a curvature thereof in the main state in the E-k diagram.

Abstract translation: 功率半导体器件可以包括具有第一导电类型的第一半导体区域; 具有第二导电类型并形成在第一半导体区域的上部的第二半导体区域; 具有第一导电类型并形成在第二半导体区域的上部的第三半导体区域; 以及通过从第三半导体区域穿透到第一半导体区域而形成的沟槽栅极。 第一半导体区域，第二半导体区域和第三半导体区域中的至少一个的一部分可以包括在Ek图中导带具有主状态和卫星状态的器件保护材料，以及曲率 处于卫星状态的器件保护材料可能低于Ek图中主状态下的曲率。

公开(公告)号：US20150270217A1

公开(公告)日：2015-09-24

申请号：US14661844

申请日：2015-03-18

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Soo KIM ,  Young Hoon KWAK ,  Chang Seob HONG ,  Joon Seok CHAE ,  Kee Ju UM

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/367

CPC classification number: H01L25/0655 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/552 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/00014

Abstract: There is provided a power module package. The power module package includes: a base substrate provided with a pattern; a heat spreader formed by being stacked on an upper surface of the base substrate; and at least one first semiconductor device mounted on an upper surface of the heat spreader, wherein an outer circumferential surface of the heat spreader is provided with a coil.

Abstract translation: 提供了一个电源模块封装。 功率模块封装包括：具有图案的基底基板; 散热器，其通过堆叠在所述基底基板的上表面上而形成; 以及安装在散热器的上表面上的至少一个第一半导体器件，其中散热器的外圆周表面设置有线圈。

公开(公告)号：US20140159104A1

公开(公告)日：2014-06-12

申请号：US13829896

申请日：2013-03-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jaehoon PARK ,  In Hyuk SONG ,  Kee Ju UM ,  Dong Soo SEO

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: There is provided a semiconductor device including: a first semiconductor region having a first conductivity; a second semiconductor region having a second conductivity and formed on a surface of the first semiconductor region; a third semiconductor region having the first conductivity and formed on a surface of the second semiconductor region; a gate electrode disposed in a trench that passes through the third semiconductor region in a depth direction and extends to an inside of the second semiconductor region; a first insulation layer formed between the gate electrode and the third semiconductor region; a second insulation layer formed between the gate electrode and the second semiconductor region; and a fourth semiconductor region having the second conductivity and formed in a portion of a surface of the third semiconductor region, wherein a thickness of a portion of the second insulation layer is greater than that of the first insulation layer.

Abstract translation: 提供了一种半导体器件，包括：具有第一导电性的第一半导体区域; 具有第二导电性并形成在第一半导体区域的表面上的第二半导体区域; 具有第一导电性并形成在第二半导体区域的表面上的第三半导体区域; 设置在沟槽中的栅电极，所述沟槽在深度方向上穿过所述第三半导体区域并延伸到所述第二半导体区域的内部; 形成在所述栅极电极和所述第三半导体区域之间的第一绝缘层; 形成在栅电极和第二半导体区之间的第二绝缘层; 以及具有第二导电性并形成在第三半导体区域的表面的一部分中的第四半导体区域，其中第二绝缘层的一部分的厚度大于第一绝缘层的厚度。

公开(公告)号：US20150187877A1

公开(公告)日：2015-07-02

申请号：US14273164

申请日：2014-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon PARK ,  Jae Kyu SUNG ,  In Hyuk SONG ,  Kee Ju UM ,  Dong Soo SEO

IPC: H01L29/08 ,  H01L29/739

CPC classification number: H01L29/407 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A power semiconductor device may include: an active region having a channel formed therein when the power semiconductor device is turned on, the channel allowing a current to flow therethrough; a termination region formed around the active region; first trenches formed in the active region, each first trench having an insulating layer formed on a surface thereof and filled with a conductive material; and second trenches formed in the termination region, each second trench having an insulating layer formed on a surface thereof and filled with a conductive material.

Abstract translation: 功率半导体器件可以包括：当功率半导体器件导通时，其中形成有沟道的有源区，允许电流流过的沟道; 形成在有源区周围的端接区域; 在有源区中形成的第一沟槽，每个第一沟槽在其表面上形成有填充有导电材料的绝缘层; 以及形成在端接区域中的第二沟槽，每个第二沟槽在其表面上形成有填充有导电材料的绝缘层。

公开(公告)号：US20150171198A1

公开(公告)日：2015-06-18

申请号：US14271244

申请日：2014-05-06

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk SONG ,  Kee Ju UM ,  Chang Su JANG ,  Jae Hoon PARK ,  Dong Soo SEO

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/7811 ,  H01L29/7813

Abstract: A power semiconductor device may include: an active region having a current flowing through a channel formed therein at the time of a turn-on operation of the power semiconductor device; a termination region formed in the vicinity of the active region; a plurality of trenches formed in a length direction of the active region; and a hole accumulating region formed in the active region and below the channel and having a first conductivity type. A trench disposed at a boundary between the termination region and the active region has a depth shallower than that of a trench adjacent thereto.

Abstract translation: 功率半导体器件可以包括：在功率半导体器件的导通操作时具有流过其中形成的沟道的电流的有源区; 形成在有源区附近的端接区域; 在所述有源区的长度方向上形成的多个沟槽; 以及形成在所述有源区域中并且在所述沟道下方并具有第一导电类型的孔积聚区域。 设置在终端区域和有源区域之间的边界处的沟槽的深度比与其相邻的沟槽的深度浅。

公开(公告)号：US20140291722A1

公开(公告)日：2014-10-02

申请号：US13937589

申请日：2013-07-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Dong Soo SEO ,  Jaehoon PARK ,  Kee Ju UM ,  Chang Su JANG ,  In Hyuk SONG

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7395 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/7397

Abstract: There is provided a power semiconductor device, including a plurality of trench gates formed to be spaced apart from each other by a predetermined distance, a current increasing part formed between the trench gates and including a first conductivity-type emitter layer and a gate oxide formed on a surface of the trench gate, and an immunity improving part formed between the trench gates and including a second conductivity-type body layer, a preventing film formed on the surface of the trench gate, and a gate oxide having a thickness less than that the gate oxide of the current increasing part.

Abstract translation: 提供了一种功率半导体器件，包括形成为彼此间隔开预定距离的多个沟槽栅极，形成在沟槽栅极之间并包括第一导电型发射极层和形成的栅极氧化物的电流增加部分 在所述沟槽栅极的表面上形成的抗扰度改善部以及形成在所述沟槽栅极之间并且包括第二导电型体层的抗扰度改善部，以及形成在所述沟槽栅极的表面上的防止膜和厚度小于所述沟槽栅极的厚度的栅极氧化物。 电流增加部分的栅极氧化物。

公开(公告)号：US20140159106A1

公开(公告)日：2014-06-12

申请号：US13874038

申请日：2013-04-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju UM ,  Dong Soo Seo ,  Chang Su Jang ,  In Hyuk Song ,  Jaehoon Park

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/423 ,  H01L29/66333

Abstract: There is provided a power semiconductor device, including: a first conductive type drift layer, a second conductive type termination layer formed on an upper portion of an edge of the drift layer, and a high concentration first conductive type channel stop layer formed on a side surface of the edge of the drift layer.

Abstract translation: 提供了一种功率半导体器件，包括：第一导电型漂移层，形成在漂移层的边缘的上部上的第二导电型端接层和形成在侧面的高浓度第一导电型沟道阻挡层 漂移层边缘的表面。

公开(公告)号：US20250168980A1

公开(公告)日：2025-05-22

申请号：US18663279

申请日：2024-05-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Min Gyu PARK ,  Jin Uk LEE ,  Kee Ju UM

IPC: H05K1/11 ,  H05K3/42

Abstract: A printed circuit board includes an insulating layer, a through-hole including a first region penetrating through a portion of the insulating layer from an upper surface of the insulating layer and a second region penetrating through another portion of the insulating layer from a lower surface of the insulating layer, and a metal via including a first metal layer disposed in a portion of the first region, a second metal layer disposed above the first metal layer and disposed in another portion of the first region, and a third metal layer disposed below the first metal layer and disposed in the second region. An upper surface of the first metal layer is located below the upper surface of the insulating layer.

公开(公告)号：US20150187882A1

公开(公告)日：2015-07-02

申请号：US14273269

申请日：2014-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon PARK ,  In Hyuk SONG ,  Chang Su JANG ,  Kee Ju UM

IPC: H01L29/16 ,  H01L29/49 ,  H01L29/51 ,  H01L21/04 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/049 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device may include: preparing a substrate formed of SiC; depositing crystalline or amorphous silicon (Si) on one surface of the substrate to form a first semiconductor layer; and performing a heat treatment under a nitrogen atmosphere to form a second semiconductor layer formed of SiCN between the substrate and the first semiconductor layer.

Abstract translation: 制造半导体器件的方法可以包括：制备由SiC形成的衬底; 在所述衬底的一个表面上沉积晶体或非晶硅（Si）以形成第一半导体层; 并在氮气气氛下进行热处理，以在衬底和第一半导体层之间形成由SiCN形成的第二半导体层。

公开(公告)号：US20150144990A1

公开(公告)日：2015-05-28

申请号：US14273378

申请日：2014-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon PARK ,  In Hyuk SONG ,  Dong Soo SEO ,  Ji Yeon OH ,  Kee Ju UM

IPC: H01L29/423 ,  H01L29/73 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/66325 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A power semiconductor device may include a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type formed on an upper portion of the first semiconductor region, a third semiconductor region having a first conductivity type formed in an inner portion of an upper portion of the second semiconductor region, a trench gate formed to penetrate from the third semiconductor region to the first semiconductor region and including a first insulating layer formed on a surface thereof, and a second insulating layer formed in a lower portion of the trench gate.

Abstract translation: 功率半导体器件可以包括具有第一导电类型的第一半导体区域，形成在第一半导体区域的上部上的具有第二导电类型的第二半导体区域，形成在内部的第一导电类型的第三半导体区域 第二半导体区域的上部的沟槽栅极，形成为从第三半导体区域穿透到第一半导体区域并且包括形成在其表面上的第一绝缘层的沟槽栅极和形成在第二半导体区域的下部的第二绝缘层 沟槽门