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公开(公告)号：US12217804B2
公开(公告)日：2025-02-04
申请号：US17960630
申请日：2022-10-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Min-Hwi Kim , Hosang Cho
Abstract: A cache read method of a nonvolatile memory device including a plurality of page buffer units and cache latches, each page buffer units having a sensing latch and a sensing node line is provided. The method comprises performing a first on-chip valley search (OVS) read on a selected memory cell using a first sensing node line and a first sensing latch of a first page buffer unit of the plurality of page buffer units; storing first data sensed from the selected memory cell in the first sensing latch, the first data based on a result of the first OVS read; dumping the first data to sensing node lines of at least one page buffer unit, excluding the first page buffer unit, from among the plurality of page buffer units; and performing a second OVS read on the selected memory cell using the first sensing latch.
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公开(公告)号：US12211559B2
公开(公告)日：2025-01-28
申请号：US17965004
申请日：2022-10-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Min-Hwi Kim , Makoto Hirano
IPC: G11C16/24 , G06F12/0802 , G11C16/04 , H10B43/27
Abstract: A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.
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23.发明公开公开(公告)号：US20240153565A1
公开(公告)日：2024-05-09
申请号：US18223278
申请日：2023-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Daeseok Byeon , Minjeong Heo
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/26
Abstract: A memory device includes a memory cell array, and a plurality of page buffer units, the page buffer units each including a sensing node, a data transfer node, a first transistor precharging the data transfer node, a second transistor connecting the sensing node to the data transfer node, a sensing latch connected to the data transfer node, a third transistor changing a data value of the sensing latch, and a fourth transistor connecting the third transistor to the data transfer node, wherein, during a sensing operation, in a first time period, the sensing node is precharged based on a first path through the first transistor, the data transfer node, and the fourth transistor, and in a second time period, a voltage of the sensing node is set to a threshold voltage according to a second path through the fourth transistor, the data transfer node, and the third transistor.
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公开(公告)号：US11942166B2
公开(公告)日：2024-03-26
申请号：US18192367
申请日：2023-03-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Bong-Kil Jung , Hangil Jeong
Abstract: An operating method of a nonvolatile memory device includes receiving, at the nonvolatile memory device, a suspend command, suspending, at the nonvolatile memory device, a program operation being performed, in response to the suspend command, receiving, at the nonvolatile memory device, a resume command, and resuming, at the nonvolatile memory device, the suspended program operation in response to the resume command. The program operation includes program loops, each of which includes a bit line setup interval, a program interval, and a verify interval. In the program interval of each of the program loops, a level of a program voltage to be applied to selected memory cells of the nonvolatile memory device increases as much as a first voltage. A difference between a level of the program voltage finally applied s suspend and a level of the program voltage applied first after resume is different from the first voltage.
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25.发明公开公开(公告)号：US20230253057A1
公开(公告)日：2023-08-10
申请号：US18192367
申请日：2023-03-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Bong-Kil Jung , Hangil Jeong
Abstract: An operating method of a nonvolatile memory device includes receiving, at the nonvolatile memory device, a suspend command, suspending, at the nonvolatile memory device, a program operation being performed, in response to the suspend command, receiving, at the nonvolatile memory device, a resume command, and resuming, at the nonvolatile memory device, the suspended program operation in response to the resume command. The program operation includes program loops, each of which includes a bit line setup interval, a program interval, and a verify interval. In the program interval of each of the program loops, a level of a program voltage to be applied to selected memory cells of the nonvolatile memory device increases as much as a first voltage. A difference between a level of the program voltage finally applied s suspend and a level of the program voltage applied first after resume is different from the first voltage.
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Patent Agency Ranking
26.发明授权公开(公告)号：US10529431B2
公开(公告)日：2020-01-07
申请号：US16296778
申请日：2019-03-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsung Cho
Abstract: A nonvolatile memory device includes a first cell string including a first dummy cell and connected to a selected string select line, a second cell string including a second dummy cell and connected to the selected string select line, a page buffer circuit configured to select one of the first and second cell strings to read data in a read operation, and a control logic circuit configured to apply a first bit line voltage to a bit line connected to the selected one of the first and second cell strings and a second bit line voltage to a bit line connected to an unselected one of the first and second cell strings in the read operation. The control logic circuit turns off the second dummy cell when the first cell string is selected and turns off the first dummy cell when the second cell string is selected.
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公开(公告)号：US20150052294A1
公开(公告)日：2015-02-19
申请号：US14458771
申请日：2014-08-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Ohsuk Kwon , Kihwan Choi
CPC classification number: G11C16/24 , G06F12/0246 , G06F2212/7201 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3459
Abstract: An operating method of a nonvolatile memory device includes receiving a read command from a memory controller; determining a read mode based on the received read command, controlling a precharge time and an offset of a precharge control signal according to the determination result, and precharging a sensing bit line among bit lines to a precharge voltage based on the controlled precharge control signal. The sensing bit line is a bit line being precharged according to the determined read mode among the bit lines.
Abstract translation: 非易失性存储器件的操作方法包括从存储器控制器接收读取命令; 基于接收到的读取命令确定读取模式，根据确定结果控制预充电控制信号的预充电时间和偏移量，以及基于受控的预充电控制信号将位线之间的感测位线预充电为预充电电压。 感测位线是根据位线中确定的读取模式预充电的位线。
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公开(公告)号：US12040799B2
公开(公告)日：2024-07-16
申请号：US18154966
申请日：2023-01-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok Nam , Jaehyuk Yang , Yongsung Cho
Abstract: A clock generating device includes a first voltage output circuit configured to output a first voltage corresponding to a power supply voltage in response to a preliminary clock signal, a clock output circuit configured to generate the preliminary clock signal and a final clock signal at a period corresponding to a difference between the first voltage and a negative feedback voltage, a negative feedback voltage generating circuit configured to generate the negative feedback voltage from a reference value corresponding to a frequency of the final clock signal and a second voltage and filtered to a uniform voltage level, and a second voltage output circuit configured to output the second voltage to the negative feedback voltage generating unit, the second voltage having lower sensitivity of fluctuations in the power supply voltage than the first voltage.
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公开(公告)号：US12002518B2
公开(公告)日：2024-06-04
申请号：US17710283
申请日：2022-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsung Cho , Kyoman Kang , Minhwi Kim , Ilhan Park , Jinyoung Chun
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/26
Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.
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公开(公告)号：US20240145013A1
公开(公告)日：2024-05-02
申请号：US18367799
申请日：2023-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung Cho , Insu Kim , Daeseok Byeon
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/30 , G11C16/3459 , G11C16/32
Abstract: A memory device includes a memory cell array, and a page buffer circuit including a plurality of page buffers selectively connected to memory cells via a plurality of bit lines, each of the plurality of page buffers including a sensing node. The sensing nodes may be charged to different levels during verification of programming states of the memory cells. For example, a first sensing node of a first page buffer connected to a first memory cell targeted for programming to a first program state from among the plurality of page buffers is precharged to a first level in a first precharge period during verification of the first program state. A second sensing node of a second page buffer connected to a second memory cell targeted for programming to a second program state charged to a second level during verification of the second program state, wherein the second level is different from the first level.
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