公开(公告)号：US20170358365A1

公开(公告)日：2017-12-14

申请号：US15181346

申请日：2016-06-13

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Gerrit Jan Hemink ,  Mohan Dunga ,  Bijesh Rajamohanan ,  Changyuan Chen

IPC: G11C16/28 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/28 ,  G06F11/1068 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/1204

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.

公开(公告)号：US20230307072A1

公开(公告)日：2023-09-28

申请号：US17701365

申请日：2022-03-22

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta ,  Gerrit Jan Hemink

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11556

Abstract: The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count of program-verify iterations since the at least one memory cell passed a verify high voltage of a previously programmed data state or discharges a sense node through a channel including the at least one memory cell and compares a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage.

公开(公告)号：US11646081B2

公开(公告)日：2023-05-09

申请号：US17392500

申请日：2021-08-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Peter Rabkin ,  Henry Chin ,  Ken Oowada ,  Dengtao Zhao ,  Gerrit Jan Hemink

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  H01L27/11565 ,  H01L25/065 ,  H01L27/11582

CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/349 ,  H01L25/0657 ,  H01L27/11565 ,  H01L27/11582 ,  H01L2225/06562

Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

公开(公告)号：US11625172B2

公开(公告)日：2023-04-11

申请号：US17349306

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G06F3/06

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

公开(公告)号：US20230076245A1

公开(公告)日：2023-03-09

申请号：US17469016

申请日：2021-09-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: An apparatus includes a control circuit configured to connect to first word lines of a first vertical sub-block and second word lines of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the first word lines in series with memory cells connected to the second word lines. The control circuit is configured to program or sense memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to second word lines that are connected to programmed memory cells and applying a second voltage to second word lines that are connected to unprogrammed memory cells.

公开(公告)号：US11551781B1

公开(公告)日：2023-01-10

申请号：US17349321

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G11C16/26 ,  G11C29/00 ,  G11C29/02 ,  G11C16/34 ,  G11C16/10

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

公开(公告)号：US11088206B2

公开(公告)日：2021-08-10

申请号：US15869573

申请日：2018-01-12

Applicant: SanDisk Technologies LLC

Inventor： Federico Nardi ,  Christopher J Petti ,  Gerrit Jan Hemink

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  G11C11/56 ,  H01L29/786

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

公开(公告)号：US20200311512A1

公开(公告)日：2020-10-01

申请号：US16901302

申请日：2020-06-15

Applicant: SanDisk Technologies LLC

Inventor： Won Ho Choi ,  Pi-Feng Chiu ,  Wen Ma ,  Minghai Qin ,  Gerrit Jan Hemink ,  Martin Lueker-Boden

IPC: G06N3/04 ,  G11C11/56 ,  G11C13/00 ,  G11C11/16 ,  G06N3/08 ,  G06N3/063 ,  G11C16/04 ,  G11C16/26

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.

公开(公告)号：US20200227125A1

公开(公告)日：2020-07-16

申请号：US16829692

申请日：2020-03-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink ,  Tai-Yuan Tseng ,  Yan Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C11/56

Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.

公开(公告)号：US10573395B1

公开(公告)日：2020-02-25

申请号：US16206718

申请日：2018-11-30

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Gerrit Jan Hemink

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/1157

Abstract: Non-volatile memory strings, which are coupled to respective bit lines and source lines, may include multiple non-volatile memory cells coupled to respective word lines. Multiple sensing operations may be used to determine data programmed into a particular non-volatile memory cell. For example, a control circuit may sense multiple values from a particular non-volatile memory cell included in a non-volatile memory string using different voltage levels on a source line coupled to the non-volatile memory string. The control circuit may select one of the multiple values based on a program state of a different non-volatile memory cell adjacent to the particular non-volatile memory cell.