公开(公告)号：US10984877B1

公开(公告)日：2021-04-20

申请号：US16717233

申请日：2019-12-17

Applicant: SanDisk Technologies LLC

Inventor： Jongyeon Kim ,  Hiroki Yabe ,  Kou Tei ,  Chia-Kai Chou ,  Ohwon Kwon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  G11C16/24

Abstract: An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.

公开(公告)号：US10885984B1

公开(公告)日：2021-01-05

申请号：US16668073

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Yuki Fujita ,  Naoki Ookuma ,  Kazuki Yamauchi ,  Masahito Takehara ,  Toru Miwa

IPC: G11C16/04 ,  G11C16/14 ,  H01L27/11524

Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.

公开(公告)号：US20190392874A1

公开(公告)日：2019-12-26

申请号：US16018571

申请日：2018-06-26

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe

IPC: G11C7/12 ,  G11C7/10 ,  G11C11/56 ,  G11C13/00 ,  G11C16/04 ,  G11C16/34

Abstract: A memory device and associated techniques improve a settling time of bit lines in a memory device during a read or verify operation. Bit line control (BLC) transistors in the sense circuits are briefly turned off during a sensing process. After the read voltage on a selected word line is changed to a second word line level or higher, a control gate voltage of the BLC transistor is lowered. This helps to inhibit a current flow from a sense circuit through a bit line when a voltage of the bit line is settling. The voltage of the bit line may be settling in response to a memory cell coupled to the selected word line undergoing a transition from off to on. A settling time of the bit line is shortened by stopping the current flow from the sense circuit. The transition of the memory cell from off to on is also improved.

公开(公告)号：US12260921B2

公开(公告)日：2025-03-25

申请号：US17838072

申请日：2022-06-10

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe

IPC: G11C16/04 ,  G11C7/06 ,  G11C7/10 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34

Abstract: Systems and methods are provided for sensing a data state of a memory cell. In an example implementation, systems and methods disclosed herein perform a method that includes connecting a first sensing node and a second sensing node to a bitline of a sensing amplifier to simultaneously discharge first and second capacitors connected to the first and second sensing nodes, respectively, through the memory cell. After a first sensing period, the second sensing node is disconnected from the bitline, which includes a first voltage level based on discharging the second capacitor. After a second sensing period, the first sensing node is disconnected from the bitline, which includes a second voltage level based on discharging the first capacitor. First and second sensing results are latched based on the first and second voltage levels, respectively, and a data state of the memory cell is based on the first and second voltage levels.

公开(公告)号：US20240250007A1

公开(公告)日：2024-07-25

申请号：US18358644

申请日：2023-07-25

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe

IPC: H01L23/498 ,  G11C7/18 ,  G11C16/28 ,  H01L23/00 ,  H01L25/065 ,  H10B43/35

CPC classification number: H01L23/49822 ,  G11C7/18 ,  G11C16/28 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0657 ,  H10B43/35 ,  H01L2224/08055 ,  H01L2224/08145 ,  H01L2224/16055 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1438 ,  H01L2924/1815

Abstract: Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

公开(公告)号：US20230343385A1

公开(公告)日：2023-10-26

申请号：US17725712

申请日：2022-04-21

Applicant: SanDisk Technologies LLC

Inventor： Hiroki Yabe

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096

Abstract: Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the second block while compensating for a difference in resistance of the first and second electrical pathways. In one aspect, the control circuit discharges a first sense node for a different period of time than a second sense node to compensate for the difference in resistance. Compensating for the difference in resistance compensates for a different IR drop of the electrical pathways.

公开(公告)号：US11573914B2

公开(公告)日：2023-02-07

申请号：US17206864

申请日：2021-03-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroki Yabe ,  Masahito Takehara

IPC: G11C7/10 ,  G06F13/16

Abstract: A data storage system includes a storage medium including a plurality of columns of memory cells, a storage controller coupled to the storage medium, and data path circuitry including a data bus coupled to the storage controller, the data bus configured to receive a plurality of bytes of data to be written to the plurality of columns of memory cells; a block of data latches having a pitch equal to a first number of bit lines of the plurality of columns of memory cells; and column redundancy circuitry configured to pass the plurality of bytes of data to the block of data latches via the plurality of columns in accordance with a nonconsecutive mapping scheme. The nonconsecutive mapping scheme includes mapping each group of three bytes to two columns by splitting one byte of each group of three bytes into two nibbles.

公开(公告)号：US20220406364A1

公开(公告)日：2022-12-22

申请号：US17349040

申请日：2021-06-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroki Yabe

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C5/06

Abstract: A flash memory die includes (i) a first subset of planes including blocks of flash memory cells connected to a first number of word line layers and a plurality of bit lines having a first length, (ii) a second subset of planes including blocks of flash memory cells connected to a second number of word line layers less than the first number of word line layers and a plurality of bit lines having a second length shorter than the first length, (iii) first peripheral circuitry implemented underneath the first subset of planes and including first sense amplifier circuitry and first peripheral control circuitry connected to the first subset of planes, and second peripheral control circuitry connected to the second subset of planes, and (iv) second peripheral circuitry implemented underneath the second subset of planes and including second sense amplifier circuitry connected to the second subset of planes.

公开(公告)号：US20220300162A1

公开(公告)日：2022-09-22

申请号：US17206864

申请日：2021-03-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroki Yabe ,  Masahito Takehara

IPC: G06F3/06 ,  G06F13/16

Abstract: A data storage system includes a storage medium including a plurality of columns of memory cells, a storage controller coupled to the storage medium, and data path circuitry including a data bus coupled to the storage controller, the data bus configured to receive a plurality of bytes of data to be written to the plurality of columns of memory cells; a block of data latches having a pitch equal to a first number of bit lines of the plurality of columns of memory cells; and column redundancy circuitry configured to pass the plurality of bytes of data to the block of data latches via the plurality of columns in accordance with a nonconsecutive mapping scheme. The nonconsecutive mapping scheme includes mapping each group of three bytes to two columns by splitting one byte of each group of three bytes into two nibbles.

公开(公告)号：US20220208270A1

公开(公告)日：2022-06-30

申请号：US17136828

申请日：2020-12-29

Applicant: SanDisk Technologies LLC

Inventor： Keiji Nose ,  Hiroki Yabe ,  Masahiro Kano ,  Yuki Fujita

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

Abstract: A method for programming three page user data in a memory array of a non-volatile memory system, comprising converting each three-bit value data pattern of the user data into a representative pair of two-bit data values, simultaneously programming two single-state memory cells with a first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of two memory cell strings, and simultaneously programming two single-state memory cells with a second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings.