公开(公告)号：US20230259300A1

公开(公告)日：2023-08-17

申请号：US17674543

申请日：2022-02-17

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Aaron Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.

公开(公告)号：US20230085776A1

公开(公告)日：2023-03-23

申请号：US17742982

申请日：2022-05-12

Applicant: SanDisk Technologies LLC

Inventor： Siddarth Naga Murty Bassa ,  YenLung Li ,  Hua-Ling Cynthia Hsu

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

公开(公告)号：US11373710B1

公开(公告)日：2022-06-28

申请号：US17165703

申请日：2021-02-02

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Yu-Chung Lien ,  Mark Murin ,  Mark Shlick

IPC: G11C5/14 ,  G11C16/30 ,  G11C16/08 ,  G11C8/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C16/10

Abstract: Time division peak power management in non-volatile memory systems is disclosed. The memory system has a memory controller and a number of semiconductor dies. Each die is assigned a time slot in which to perform high current portions of memory operations. The memory controller provides an external clock to each die. Each die tracks repeating time slots based on the external clock. The memory controller may synchronize this tracking. If a die is about to perform a high current portion of a memory operation, the die checks to determine if its allocated slot has been reached. If not, the die halts the memory operation until its allocated time slot is reached. When the allocated time slot is reached, the halted memory operation is resumed at the high current portion. Therefore, the high current portion of the memory operation occurs during the allocated time slot.

公开(公告)号：US11226772B1

公开(公告)日：2022-01-18

申请号：US16912381

申请日：2020-06-25

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Mark Murin ,  Hua-Ling Cynthia Hsu ,  Tomer Eliash ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/32 ,  H01L25/065 ,  G11C16/04

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

公开(公告)号：US12057188B2

公开(公告)日：2024-08-06

申请号：US17742982

申请日：2022-05-12

Applicant: SanDisk Technologies LLC

Inventor： Siddarth Naga Murty Bassa ,  YenLung Li ,  Hua-Ling Cynthia Hsu

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C7/065 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

公开(公告)号：US12009049B2

公开(公告)日：2024-06-11

申请号：US17900066

申请日：2022-08-31

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li ,  Siddarth Naga Murty Bassa ,  Jeongduk Sohn

IPC: G11C7/10

CPC classification number: G11C7/1057 ,  G11C7/1048 ,  G11C2207/101

Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches.

公开(公告)号：US11966621B2

公开(公告)日：2024-04-23

申请号：US17674543

申请日：2022-02-17

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Aaron Lee

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203

Abstract: Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.

公开(公告)号：US20240071482A1

公开(公告)日：2024-02-29

申请号：US17895304

申请日：2022-08-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Hua-Ling Cynthia Hsu

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459

Abstract: Technology is disclosed herein for mixed lockout verify. In a first programming phase, prior to a pre-determined data state completing verification, a no-lockout program verify is performed. After the pre-determined data state has completed verification, a lockout program verify is performed. The no-lockout verify may include charging all bit lines associated with the group to a sensing voltage to perform. The lockout verify may include selectively charging to the sensing voltage only bit lines associated with memory cells in the group to be verified. Bit lines associated with memory cells in the group that are not to be verified may be grounded to perform the lockout verify. The lockout verify saves considerable current and/or power. However, performing the lockout verify during the first programming phase may slow performance due to a need to scan the content in a remote set of data latches.

公开(公告)号：US20240071433A1

公开(公告)日：2024-02-29

申请号：US17900066

申请日：2022-08-31

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li ,  Siddarth Naga Murty Bassa ,  Jeongduk Sohn

IPC: G11C7/10

CPC classification number: G11C7/1057 ,  G11C7/1048 ,  G11C2207/101

Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches.

公开(公告)号：US11901019B2

公开(公告)日：2024-02-13

申请号：US17666657

申请日：2022-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hua-Ling Cynthia Hsu ,  Masaaki Higashitani ,  YenLung Li ,  Chen Chen

IPC: G11C16/26 ,  G11C16/24 ,  H03M13/00 ,  H03M13/11 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24 ,  H03M13/1111 ,  H03M13/611

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.