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    Apparatus and methods for smart verify with adaptive voltage offset
    21.
    发明授权
    Apparatus and methods for smart verify with adaptive voltage offset 有权

    公开(公告)号：US12293797B2

    公开(公告)日：2025-05-06

    申请号：US18355343

    申请日：2023-07-19

    Applicant: SanDisk Technologies LLC

    Inventor： Longju Liu ,  Sarath Puthenthermadam ,  Jiahui Yuan

    IPC: G11C16/10 ,  G11C16/34

    Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

    Temperature compensation for unselected sub-block inhibit bias for mitigating erase disturb
    23.
    发明授权
    Temperature compensation for unselected sub-block inhibit bias for mitigating erase disturb 有权

    公开(公告)号：US11636905B2

    公开(公告)日：2023-04-25

    申请号：US17113920

    申请日：2020-12-07

    Applicant: SanDisk Technologies LLC

    Inventor： Sarath Puthenthermadam ,  Huai-yuan Tseng

    IPC: G11C16/16 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11556

    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block having memory cells connected to word lines and arranged in strings and is divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The apparatus has a temperature measuring circuit configured to detect an ambient temperature of the apparatus. A control circuit is configured to determine a word line inhibit voltage based on the ambient temperature. The control circuit applies an erase voltage to each of the strings while simultaneously applying a word line erase voltage to the word lines associated with a selected one of the first and second sub-blocks to encourage erasing and the word line inhibit voltage to the word lines associated with an unselected one of the first and second sub-blocks to discourage erasing in the erase operation.

    Hole pre-charge scheme using gate induced drain leakage generation
    24.
    发明授权
    Hole pre-charge scheme using gate induced drain leakage generation 有权

    公开(公告)号：US11211392B1

    公开(公告)日：2021-12-28

    申请号：US16916186

    申请日：2020-06-30

    Applicant: SanDisk Technologies LLC

    Inventor： Sarath Puthenthermadam ,  Yanli Zhang ,  Huai-yuan Tseng ,  Peng Zhang

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/06 ,  G11C5/06 ,  G11C5/02

    Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

    Peak and average current reduction for sub block memory operation
    25.
    发明授权
    Peak and average current reduction for sub block memory operation 有权

    公开(公告)号：US11189351B2

    公开(公告)日：2021-11-30

    申请号：US16832293

    申请日：2020-03-27

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Sarath Puthenthermadam ,  Huai-Yuan Tseng

    IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11582

    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.

    PEAK AND AVERAGE CURRENT REDUCTION FOR SUB BLOCK MEMORY OPERATION
    26.
    发明申请
    PEAK AND AVERAGE CURRENT REDUCTION FOR SUB BLOCK MEMORY OPERATION 有权

    公开(公告)号：US20210304822A1

    公开(公告)日：2021-09-30

    申请号：US16832293

    申请日：2020-03-27

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Sarath Puthenthermadam ,  Huai-Yuan Tseng

    IPC: G11C16/26 ,  G11C16/04

    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.

    Fast detection of defective memory block to prevent neighbor plane disturb
    27.
    发明授权
    Fast detection of defective memory block to prevent neighbor plane disturb 有权

    公开(公告)号：US10529435B2

    公开(公告)日：2020-01-07

    申请号：US15863404

    申请日：2018-01-05

    Applicant: SanDisk Technologies LLC

    Inventor： Sarath Puthenthermadam ,  Deepanshu Dutta ,  Long Pham

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/32 ,  G11C16/04

    Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.

    Dynamic anneal characteristics for annealing non-volatile memory
    28.
    发明授权
    Dynamic anneal characteristics for annealing non-volatile memory 有权

    公开(公告)号：US10467134B2

    公开(公告)日：2019-11-05

    申请号：US15247910

    申请日：2016-08-25

    Applicant: SanDisk Technologies LLC

    Inventor： Navneeth Kankani ,  Linh Truong ,  Sarath Puthenthermadam ,  Deepanshu Dutta

    IPC: G06F12/02

    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for annealing non-volatile memory. A controller identifies one or more life cycle characteristics of a non-volatile storage element. The controller selects an anneal duration and an anneal temperature for annealing the non-volatile storage element. The anneal duration and the anneal temperature are based on the one or more life cycle characteristics. The controller anneals the non-volatile storage element using the selected anneal duration and anneal temperature.

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