公开(公告)号：US11521686B2

公开(公告)日：2022-12-06

申请号：US17218498

申请日：2021-03-31

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Hua-Ling Hsu ,  Huai-Yuan Tseng ,  Fanglin Zhang

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.

公开(公告)号：US11475958B2

公开(公告)日：2022-10-18

申请号：US17192598

申请日：2021-03-04

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-yuan Tseng ,  Swaroop Kaza ,  Tomer Eliash

IPC: G11C11/00 ,  G11C16/10 ,  G11C16/30 ,  G11C16/24 ,  G11C16/26

Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

公开(公告)号：US11456333B2

公开(公告)日：2022-09-27

申请号：US16903654

申请日：2020-06-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Deepanshu Dutta ,  Christopher Petti

IPC: G11C11/16 ,  H01L27/24 ,  H01L43/12 ,  H01L45/00 ,  G11C13/00 ,  H01L43/02 ,  H01L27/22 ,  G11C16/04

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.

公开(公告)号：US11386968B1

公开(公告)日：2022-07-12

申请号：US17149136

申请日：2021-01-14

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-yuan Tseng ,  Tomer Eliash

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/12 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/24

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus also includes a control circuit coupled to the word lines and the bit lines and configured to determine whether a program operation of the memory cells involves all of the plurality of planes. In response to the program operation of the memory cells not involving all of the plurality of planes, the control circuit adjusts at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation based on a quantity of the plurality of planes associated with the memory cells being program-verified in the program operation.

公开(公告)号：US11385810B2

公开(公告)日：2022-07-12

申请号：US16916620

申请日：2020-06-30

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G06F3/06

Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.

公开(公告)号：US10727276B1

公开(公告)日：2020-07-28

申请号：US16422187

申请日：2019-05-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Deepanshu Dutta ,  Christopher Petti

IPC: H01L27/24 ,  H01L43/12 ,  H01L45/00 ,  G11C13/00 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.

公开(公告)号：US12249378B2

公开(公告)日：2025-03-11

申请号：US17666810

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

公开(公告)号：US11972814B2

公开(公告)日：2024-04-30

申请号：US17701320

申请日：2022-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Ravi Kumar ,  Jiahui Yuan ,  Bo Lei ,  Zhenni Wan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

公开(公告)号：US11699494B2

公开(公告)日：2023-07-11

申请号：US17340826

申请日：2021-06-07

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Deepanshu Dutta ,  Huai-yuan Tseng ,  Ravi Kumar

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C2216/16

Abstract: A method for programming a memory block of a non-volatile memory structure, wherein the method provides, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.

公开(公告)号：US20230066972A1

公开(公告)日：2023-03-02

申请号：US17410265

申请日：2021-08-24

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Henry Chin ,  Erika Penzo

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.