公开(公告)号：US20210265353A1

公开(公告)日：2021-08-26

申请号：US17256349

申请日：2019-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru OKAMOTO ,  Ryo TOKUMARU ,  Ryota HODO

IPC: H01L27/108 ,  H01L29/786 ,  G11C11/402

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; a third conductor including a region that is over the oxide and overlaps with a region between the first conductor and the second conductor; a first insulator over the third conductor; a fourth conductor that is electrically connected to the first conductor through a first opening provided in the first insulator; a second insulator that is provided over the first insulator and that is provided over the fourth conductor in the first opening; a fifth conductor overlapping with the fourth conductor with the second insulator positioned therebetween in the first opening; and a sixth conductor electrically connected to the second conductor in a second opening provided in the first insulator and the second insulator. The fifth conductor and the sixth conductor are in contact with a top surface of the second insulator over the first insulator.

公开(公告)号：US20210074834A1

公开(公告)日：2021-03-11

申请号：US17073639

申请日：2020-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru OKAMOTO ,  Shinya SASAGAWA

IPC: H01L29/66 ,  H01L21/385 ,  H01L29/786 ,  H01L27/12 ,  H01L29/22 ,  H01L29/24 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

公开(公告)号：US20190237584A1

公开(公告)日：2019-08-01

申请号：US16378622

申请日：2019-04-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshinobu ASAMI ,  Yutaka OKAZAKI ,  Satoru OKAMOTO ,  Shinya SASAGAWA

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/475 ,  H01L29/423 ,  H01L29/06 ,  C23C16/455 ,  C23C16/40 ,  H01L21/4757 ,  H01L21/67

CPC classification number: H01L29/7869 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/67207 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78696

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

公开(公告)号：US20170062619A1

公开(公告)日：2017-03-02

申请号：US15235242

申请日：2016-08-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Takashi HAMADA ,  Akihisa SHIMOMURA ,  Satoru OKAMOTO ,  Katsuaki TOCHIBAYASHI

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/4763 ,  H01L21/465 ,  H01L29/423 ,  H01L21/4757

CPC classification number: H01L29/7869 ,  H01L21/465 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

Abstract translation: 提供一分钟晶体管。 提供具有低寄生电容的晶体管。 提供具有高频特性的晶体管。 提供具有高导通状态电流的晶体管。 提供包括晶体管的半导体器件。 提供了具有高集成度的半导体器件。 一种包括氧化物半导体的半导体器件; 第二绝缘体; 第二导体 第三导体; 第四导体 第五个指挥 嵌入在形成于第二绝缘体的开口部的第一导体和第一绝缘体，第二导​​体，第三导体，第四导体和第五导体; 第二导体的侧表面和底表面与第四导体接触的区域; 以及第三导体的侧表面和底表面与第五导体接触的区域。

公开(公告)号：US20170012139A1

公开(公告)日：2017-01-12

申请号：US15193564

申请日：2016-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L21/321 ,  H01L21/306

CPC classification number: H01L29/78693 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.

Abstract translation: 提供一分钟晶体管。 提供具有小寄生电容的晶体管。 提供了具有高频特性的晶体管。 提供包括晶体管的半导体器件。 半导体器件包括氧化物半导体，第一导体和嵌入第一绝缘体中的第二绝缘体，第二导​​体和第三导体。 第二导体和第三导体彼此面对的边缘具有30度以上且90度以下的锥角。

公开(公告)号：US20160218219A1

公开(公告)日：2016-07-28

申请号：US14995562

申请日：2016-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinobu ASAMI ,  Yutaka OKAZAKI ,  Satoru OKAMOTO ,  Shinya SASAGAWA

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/475 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7869 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/67207 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78696

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

Abstract translation: 半导体器件包括在第一绝缘层上的第一氧化物绝缘层，在第一氧化物绝缘层上的氧化物半导体层，氧化物半导体层上的源电极层和漏电极层，在源电极层上的第二绝缘层 漏极电极层，氧化物半导体层上的第二氧化物绝缘层，第二氧化物绝缘层上的栅极绝缘层，栅极绝缘层上的栅极电极层和第二绝缘层上的第三绝缘层， 第二氧化物绝缘层，栅极绝缘层和栅极电极层。 第二绝缘层的侧表面部分与第二氧化物绝缘层接触。 栅极电极层包括第一区域和第二区域。 第一区域的宽度大于第二区域的宽度。

公开(公告)号：US20220367509A1

公开(公告)日：2022-11-17

申请号：US17623301

申请日：2020-06-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Satoru OKAMOTO

IPC: H01L27/11582

Abstract: A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening; a first conductor including a second opening over the first insulator; a second insulator including a third opening over the first conductor; a third insulator provided along a first side surface of the first opening, a second side surface of the second opening, and a third side surface of the third opening; an oxide provided along the first side surface, the second side surface, and the third side surface with the third insulator therebetween; a second conductor provided at the first side surface with the third insulator and the oxide therebetween; and a third conductor provided at the third side surface with the third insulator and the oxide therebetween, the oxide includes a first region in the first opening, a second region in the second opening, and a third region in the third opening, and the second region has higher resistance than the first region and the third region.

公开(公告)号：US20220351509A1

公开(公告)日：2022-11-03

申请号：US17619623

申请日：2020-06-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro KANEMURA ,  Taisuke HIGASHI ,  Hiroya HIBINO ,  Atsuya TOKINOSU ,  Hiromichi GODO ,  Satoru OKAMOTO

IPC: G06V20/20 ,  G06F1/16 ,  G06V20/68 ,  G09B5/02

Abstract: A data processing system, a data processing device, and a data processing method are provided. The data processing system includes a wearable device including a display means and an imaging means and a database that is connected to the wearable device through a network. The database includes at least one of pieces of information on a cooking recipe, a cooking method, and a material. The wearable device detects a first material by the imaging means. The wearable device collects information on the first material from the database. When the first material exists in a specific region in an imaging range of the imaging means, the information on the first material is displayed on the display means. When the first material does not exist in the specific region, the information on the first material is not displayed on the display means.

公开(公告)号：US20210288077A1

公开(公告)日：2021-09-16

申请号：US17329250

申请日：2021-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota HODO ,  Motomu KURATA ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/467 ,  H01L21/463 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

公开(公告)号：US20190189643A1

公开(公告)日：2019-06-20

申请号：US16280792

申请日：2019-02-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota HODO ,  Motomu KURATA ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L21/463 ,  H01L21/467 ,  H01L21/768 ,  H01L29/786 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/1225 ,  H01L21/02565 ,  H01L21/463 ,  H01L21/467 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.