公开(公告)号：US20160217848A1

公开(公告)日：2016-07-28

申请号：US14993375

申请日：2016-01-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Wataru UESUGI ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G06F2212/221 ,  G11C5/14 ,  G11C5/148 ,  G11C11/418 ,  G11C14/0054 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.

Abstract translation: 提供具有新颖结构的半导体器件。 提供一种降低功耗的半导体器件。 包括能够将数据备份到非易失性存储器的SRAM和存储器单元的外围电路的存储单元被配置为提供不同的功率门控状态。 在非常短的第一时段中，通过关闭开关使位线进入电浮动状态。 在比第一期间长的第二期间，对存储单元进行电力门控。 在比第二时段长的第三时段中，对存储单元和外围电路进行功率门控。

公开(公告)号：US20160203852A1

公开(公告)日：2016-07-14

申请号：US15072432

申请日：2016-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Naoaki TSUTSUI ,  Atsuo ISOBE ,  Wataru UESUGI ,  Takuro OHMARU

IPC: G11C11/4093

CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。

公开(公告)号：US20160149573A1

公开(公告)日：2016-05-26

申请号：US14944262

申请日：2015-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yukio MAEHASHI ,  Wataru UESUGI

IPC: H03K19/00 ,  H03K3/356

CPC classification number: H03K19/0013 ,  G11C5/141 ,  G11C5/148 ,  G11C7/222 ,  G11C11/24 ,  G11C11/34 ,  G11C14/0054 ,  G11C19/184 ,  G11C19/28 ,  H03K3/012 ,  H03K3/356008 ,  H03K3/356104 ,  H03K3/356139 ,  H03K3/356156 ,  H03K3/356173 ,  H03K3/356191 ,  H03K3/35625 ,  H03K19/01855 ,  H03K19/173 ,  H03K19/177

Abstract: A logic circuit that can retain a state even without power supply is provided. The logic circuit includes a first circuit, a pair of retention circuits, and a second circuit. The pair of retention circuits includes two switches electrically connected to each other in series and a capacitor electrically connected to a connection portion of the two switches. Each of the two switches is formed using an oxide semiconductor transistor. The first circuit has a function of generating complementary data from a piece of input data. The pair of retention circuits retains the complementary data. The second circuit has a function of amplifying the complementary data retained in the pair of retention circuits.

Abstract translation: 提供了即使没有电源也能保持状态的逻辑电路。 逻辑电路包括第一电路，一对保持电路和第二电路。 一对保持电路包括串联电连接的两个开关和电连接到两个开关的连接部分的电容器。 两个开关中的每一个都使用氧化物半导体晶体管形成。 第一电路具有从一条输入数据产生互补数据的功能。 该对保持电路保留补充数据。 第二电路具有放大保持在一对保持电路中的互补数据的功能。

公开(公告)号：US20160104521A1

公开(公告)日：2016-04-14

申请号：US14872535

申请日：2015-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Wataru UESUGI ,  Takahiko ISHIZU

IPC: G11C11/4091

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2213/71 ,  H01L27/10808

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

Abstract translation: 提供具有低功耗的半导体器件或具有减小的面积的半导体器件。 半导体器件包括具有第一存储单元和第二存储单元的单元阵列; 以及包括第一读出放大器和第二读出放大器的读出放大器电路。 单元阵列位于读出放大器电路之上。 第一读出放大器通过第一布线BL与第一存储单元电连接。 第二读出放大器通过第二布线BL与第二存储单元电连接。 第一读出放大器和第二读出放大器电连接到布线GBL。 感测放大器电路被配置为选择第一布线BL的电位和第二布线BL的电位中的一个，并将所选择的电位输出到布线GBL。

公开(公告)号：US20160006433A1

公开(公告)日：2016-01-07

申请号：US14755906

申请日：2015-06-30

Applicant: Semiconductor Energy Laboratory Co.,Ltd.

Inventor： Takahiko ISHIZU ,  Wataru UESUGI

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H03K19/0008

Abstract: A semiconductor device with a novel structure is provided. In the semiconductor device executing a pipeline processing, a first arithmetic unit and a second arithmetic unit are provided for an execution stage, and transistors for performing power gating for the respective arithmetic units are provided. Only the arithmetic unit that performs an arithmetic operation is supplied with power supply voltage. Thus, fine-grained power gating can be performed, so that the power consumption of the semiconductor device can be reduced. In each of the transistors for performing power gating, a channel formation region includes an oxide semiconductor; thus, a reduction in leakage current between power supply lines can be achieved. Furthermore, these transistors and transistors in the arithmetic units can be provided in different layers, and thus an increase in area overhead due to the additionally provided transistors can be prevented.

Abstract translation: 提供具有新颖结构的半导体器件。 在执行流水线处理的半导体装置中，设置有用于执行级的第一运算单元和第二运算单元，并且提供用于对各运算单元进行功率选通的晶体管。 只有执行算术运算的算术单元被供给电源电压。 因此，可以进行细粒度的电源门控，从而可以降低半导体器件的功耗。 在用于执行电源门控的每个晶体管中，沟道形成区域包括氧化物半导体; 因此，可以实现电源线之间的漏电流的减小。 此外，这些运算单元中的这些晶体管和晶体管可以设置在不同的层中，因此可以防止由于额外提供的晶体管而导致的面积开销的增加。

公开(公告)号：US20150269977A1

公开(公告)日：2015-09-24

申请号：US14659914

申请日：2015-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Wataru UESUGI

IPC: G11C5/14 ,  G11C11/409 ,  G11C11/4074

CPC classification number: G11C5/147 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G11C11/419 ,  G11C14/0054

Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

Abstract translation: 提供一种具有存储单元阵列的半导体器件，其能够根据对存储单元阵列的非访问周期而存在于三个电源门控状态。 存储单元阵列包括多个存储单元，每个存储单元具有SRAM和非易失性存储器部分，其具有在通道区域中具有氧化物半导体的晶体管。 三个电源门控状态包括：执行到存储器单元阵列的电源门控的第一状态; 在存储单元阵列上执行功率门控的第二状态和控制存储单元阵列的外围电路; 以及第三状态，其中除了存储单元阵列和外围电路之外，电源电压供应电路经受电源门控。