公开(公告)号：US20180232302A1

公开(公告)日：2018-08-16

申请号：US15950210

申请日：2018-04-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Naoaki TSUTSUI

IPC: G06F12/02 ,  H02J13/00 ,  H02J1/00 ,  H01L27/06 ,  H01L27/11 ,  H01L27/1156

CPC classification number: G06F12/02 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1156 ,  H02J1/00 ,  H02J13/0003

Abstract: A novel semiconductor device or a semiconductor device whose power consumption can be reduced is provided. The semiconductor device includes a sensor portion, a memory portion, and a control portion. The memory portion has functions of storing multiple detection data and sending them to the control portion. Therefore, a certain amount of detection data acquired through sensing by the sensor portion can be held, and the detection data can be sent to the control portion at a desired timing. Accordingly, in the semiconductor device, the control portion does not need to operate every time information is acquired, and thus, the power supply to the control portion can be completely or partially stopped.

公开(公告)号：US20170330873A1

公开(公告)日：2017-11-16

申请号：US15667672

申请日：2017-08-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA ,  Naoaki TSUTSUI ,  Atsuo ISOBE

IPC: H01L27/02 ,  H01L29/786 ,  H01L27/12 ,  H01L27/06 ,  H01L23/528 ,  H01L23/532 ,  H03K19/00

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1274 ,  H01L29/7869 ,  H03K19/0008

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

公开(公告)号：US20160351243A1

公开(公告)日：2016-12-01

申请号：US15160076

申请日：2016-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Yutaka SHIONOIRI ,  Naoaki TSUTSUI ,  Shunpei YAMAZAKI

IPC: G11C11/40 ,  H01L27/12 ,  G11C5/06 ,  G11C7/12 ,  G11C8/08 ,  H01L23/528 ,  H01L27/105 ,  G11C11/24

CPC classification number: H01L27/1207 ,  G11C5/063 ,  G11C11/401 ,  G11C11/4097 ,  G11C2029/0403 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255

Abstract: A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.

Abstract translation: 一种其中薄膜数量减少的存储器件。 存储器件包括电路和布线。 电路包括第一存储单元和第二存储单元。 第一存储单元包括第一晶体管，第二晶体管和第一电容器。 第二存储单元包括第三晶体管，第四晶体管和第二电容器。 第二存储单元堆叠在第一存储单元上。 第一晶体管的源极和漏极之一电连接到第二晶体管的栅极和第一电容器。 第三晶体管的源极和漏极之一电连接到第四晶体管和第二电容器的栅极。 第一晶体管的栅极和第三晶体管的栅极电连接到布线。

公开(公告)号：US20160350182A1

公开(公告)日：2016-12-01

申请号：US15162035

申请日：2016-05-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Naoaki TSUTSUI

IPC: G06F11/10 ,  G11C7/22 ,  G11C5/06 ,  G11C29/52 ,  G11C7/12

CPC classification number: G06F11/1052 ,  G11C11/405 ,  G11C11/408 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4016 ,  H01L27/10814 ,  H01L27/1225

Abstract: A memory system that includes an error check and correct (ECC) circuit is provided. The memory system includes a memory, a circuit, and a processor. The memory system has a function of receiving write data from the outside. The memory includes a user data region, a first management region, and a second management region. The user data region stores the write data. The circuit has a function of performing ECC processings on the write data read from the user data region. The first management region stores data that indicates whether the user data region has stored the write data or not. The second management region stores data that indicates whether the circuit has performed the ECC processings on the write data read from the user data region or not.

Abstract translation: 提供了包括错误检查和正确（ECC）电路的存储器系统。 存储器系统包括存储器，电路和处理器。 存储器系统具有从外部接收写入数据的功能。 存储器包括用户数据区域，第一管理区域和第二管理区域。 用户数据区存储写入数据。 电路具有对从用户数据区域读取的写入数据执行ECC处理的功能。 第一管理区域存储指示用户数据区域是否存储了写入数据的数据。 第二管理区域存储指示电路是否对从用户数据区域读取的写入数据执行ECC处理的数据。

公开(公告)号：US20250110763A1

公开(公告)日：2025-04-03

申请号：US18897744

申请日：2024-09-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Naoaki TSUTSUI ,  Ryo NAKAZATO

IPC: G06F9/455 ,  G06F9/30

Abstract: A novel data processing system composed of three data processing devices is provided. A first data processing device receives an instruction sentence, generates a processing result, and transmits the result including an intermediate code. A second data processing device receives a document, the processing result, and model data, generates the instruction sentence, and transmits the instruction sentence. The instruction sentence includes instructions relating to analysis of the document, extraction of a processing step, and conversion into the intermediate code. The second data processing device extracts the intermediate code from the processing result and transmits the intermediate code. A third data processing device receives the intermediate code, simulates the processing step in accordance with the intermediate code, and generates and transmits the model data.

公开(公告)号：US20160178409A1

公开(公告)日：2016-06-23

申请号：US14971636

申请日：2015-12-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Naoaki TSUTSUI

IPC: G01D9/32 ,  H02J1/00 ,  H01L29/786

CPC classification number: G06F12/02 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1156 ,  H02J1/00 ,  H02J13/0003

Abstract: A novel semiconductor device or a semiconductor device whose power consumption can be reduced is provided. The semiconductor device includes a sensor portion, a memory portion, and a control portion. The memory portion has functions of storing multiple detection data and sending them to the control portion. Therefore, a certain amount of detection data acquired through sensing by the sensor portion can be held, and the detection data can be sent to the control portion at a desired timing. Accordingly, in the semiconductor device, the control portion does not need to operate every time information is acquired, and thus, the power supply to the control portion can be completely or partially stopped.

Abstract translation: 提供了可以降低功耗的新颖的半导体器件或半导体器件。 半导体器件包括传感器部分，存储器部分和控制部分。 存储器部分具有存储多个检测数据并将其发送到控制部分的功能。 因此，可以保持通过传感器部分的感测获取的一定量的检测数据，并且可以在期望的时刻将检测数据发送到控制部分。 因此，在半导体装置中，控制部在每次获取信息时都不需要动作，能够完全或部分停止对控制部的供电。

公开(公告)号：US20250147994A1

公开(公告)日：2025-05-08

申请号：US18930010

申请日：2024-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Naoaki TSUTSUI ,  Toshiki HAMADA

IPC: G06F16/33 ,  G06F16/35 ,  G06F40/186

Abstract: A novel information processing system that is highly convenient, useful, or reliable is provided. The information processing system includes a first component, a second component, and a third component. The first component has a function of receiving a text written in a natural language and a query for performing retrieval in design assets and transferring the text and the query to the third component, a function of providing a code, and a function of emphasizing a portion related to the code and then providing the design assets. The second component has a function of generating an intermediate code from the text in accordance with a prompt and transferring the intermediate code to the third component. The third component has a function of classifying the text into a predetermined class, generating the prompt, and transferring the prompt to the second component. The third component has a function of generating the code from the command using the received intermediate code as an argument in accordance with the syntax, and transferring the code to the first component.

公开(公告)号：US20200184137A1

公开(公告)日：2020-06-11

申请号：US16622054

申请日：2018-06-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Naoaki TSUTSUI ,  Yusuke KOUMURA ,  Yuji IWAKI ,  Shunpei YAMAZAKI

IPC: G06F30/392 ,  G06N3/08 ,  G06N3/04 ,  G06F30/27

Abstract: To perform layout design for a small area satisfying a design rule, within a short period of time. A layout design system which includes a processing portion and in which a circuit diagram and layout design information are input to the processing portion, the processing portion has a function of generating layout data from the circuit diagram and the layout design information by performing Q learning, the processing portion has a function of outputting the layout data, the processing portion includes a first neural network, and the first neural network estimates an action value function in the Q learning.

公开(公告)号：US20160203852A1

公开(公告)日：2016-07-14

申请号：US15072432

申请日：2016-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Naoaki TSUTSUI ,  Atsuo ISOBE ,  Wataru UESUGI ,  Takuro OHMARU

IPC: G11C11/4093

CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。

公开(公告)号：US20140204645A1

公开(公告)日：2014-07-24

申请号：US14157574

申请日：2014-01-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro OHMARU ,  Naoaki TSUTSUI

IPC: G11C11/407

CPC classification number: G11C29/00 ,  G01R31/318597

Abstract: To supply a signal in which the occurrence of delays is prevented to a storage circuit. To provide a novel semiconductor device in which a load applied to a logic circuit is low. The following structure is completed: a storage circuit to which a plurality of data signals and a selection signal are supplied connects two combination circuits, and a storage circuit has a function of selecting one of a plurality of data signals in accordance with the selection signal. A selection circuit is not necessarily provided between the storage circuit and the combination circuit. As a result, the combination circuit can supply a signal in which the occurrence of delays is prevented to the storage circuit.

Abstract translation: 提供一种信号，其中阻止发生延迟到存储电路。 提供一种新颖的半导体器件，其中施加到逻辑电路的负载较低。 完成以下结构：提供多个数据信号和选择信号的存储电路连接两个组合电路，并且存储电路具有根据选择信号选择多个数据信号中的一个的功能。 在存储电路和组合电路之间不一定设置选择电路。 结果，组合电路可以向存储电路提供阻止发生延迟的信号。