-
公开(公告)号：US11081150B2
公开(公告)日：2021-08-03
申请号：US16439452
申请日：2019-06-12
Applicant: SK hynix Inc.
Inventor： Sang Gu Jo , Donggun Kim , Yong Ju Kim , Do-Sun Hong
Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.
-
公开(公告)号：US10557888B2
公开(公告)日：2020-02-11
申请号：US15650403
申请日：2017-07-14
Inventor： Chul Woo Kim , Dong Yoon Kim , In Hwa Jung , Yong Ju Kim
IPC: G01R31/319 , G06F11/22 , G01R31/28 , G01R31/3167
Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.
-
公开(公告)号：US10261860B2
公开(公告)日：2019-04-16
申请号：US15611151
申请日：2017-06-01
Applicant: SK hynix Inc.
Inventor： Sungeun Lee , Jung Hyun Kwon , Yong Ju Kim , Jae Sun Lee , Jingzhe Xu
Abstract: A semiconductor system includes a host and a media controller. The host may generate first host parities from first host data based on an error check matrix. The media controller may include a first input/output (I/O) circuit and a second I/O circuit. The media controller may generate first media data and first media parities based on the first host data and the first host parities. The first I/O circuit may generate, based on the error check matrix, first internal data by correcting errors in the first host data using the first host parities. The second I/O circuit may generate the first media data and the first media parities from the first internal data.
-
Patent Agency Ranking
公开(公告)号：US10198184B2
公开(公告)日：2019-02-05
申请号：US15434784
申请日：2017-02-16
Applicant: SK hynix Inc.
Inventor： Do-Sun Hong , Donggun Kim , Yong Ju Kim , Sang Gu Jo
Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write access for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.
-
公开(公告)号：US10108250B2
公开(公告)日：2018-10-23
申请号：US15230734
申请日：2016-08-08
Applicant: SK hynix Inc.
Inventor： Yong Ju Kim , Jung Hyun Kwon , Donggun Kim , Sungeun Lee , Jae Sun Lee , Sang Gu Jo , Jingzhe Xu , Do Sun Hong
IPC: G06F1/32 , G06F12/02 , G06F12/1009 , G06F12/121 , G11C11/4074 , G11C11/4091 , G11C11/406
Abstract: In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.
-
26.发明授权公开(公告)号：US08837239B2
公开(公告)日：2014-09-16
申请号：US13797574
申请日：2013-03-12
Inventor： Jong Gon Jung , Yong Sam Moon , Yong Ju Kim , Jong Ho Jung
CPC classification number: G11C7/222 , G11C2207/2272
Abstract: A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.
Abstract translation: 延迟控制电路包括：时钟延迟，被配置为输出通过以相同间隔串行延迟输入时钟信号而获得的多个串行延迟信号;偏差信息生成单元，被配置为基于延迟值生成偏差信息， 时钟信号经历芯片，等待时间信息，时钟选择器，被配置为基于多个串行延迟信号和偏差信息输出多个时钟选择信号;命令信号处理单元，被配置为基于 输入命令信号，并通过可变地延迟读取信号来输出可变延迟复制信号;以及等待时间移位器，被配置为通过将多个时钟选择信号与可变延迟复制信号组合来输出等待时间信号。
-
27.发明授权公开(公告)号：US08816734B2
公开(公告)日：2014-08-26
申请号：US13711692
申请日：2012-12-12
Applicant: SK hynix Inc.
Inventor： Jae Min Jang , Yong Ju Kim , Dae Han Kwon , Hae Rang Choi
IPC: H03L7/06
CPC classification number: H03H11/265 , H03L7/06 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/085
Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.
Abstract translation: 时钟生成电路包括延迟线，延迟建模块，相位检测块，多更新信号生成块和延迟线。 延迟线延迟输入时钟并产生延迟时钟。 延迟建模块通过建模延迟值将延迟时钟延迟并产生反馈时钟。 相位检测块比较输入时钟和反馈时钟的相位，并产生相位信息，并量化输入时钟和反馈时钟之间的相位差，并产生相位代码。 多更新信号生成块响应于相位代码生成多更新信号。 响应于多更新信号和相位信息，延迟线控制块改变延迟线的延迟量。
-
公开(公告)号：US08773180B2
公开(公告)日：2014-07-08
申请号：US13720943
申请日：2012-12-19
Applicant: SK hynix Inc.
Inventor： Jae Min Jang , Yong Ju Kim , Dan Han Kwon , Hae Rang Choi
IPC: H03L7/00
Abstract: A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.
Abstract translation: 复位信号发生装置包括复位信号生成单元和复位信号扩展单元。 复位信号生成单元响应于复位输入信号启用复位信号和使能信号，并且响应于脉冲宽度扩展信号而禁用复位信号。 复位信号扩展单元响应于使能信号产生使能了预定时间的脉宽扩展信号。
-
-
-
-
-
-
-
Search Results
28
records
(took 0.017 seconds)
