公开(公告)号：US20200295138A1

公开(公告)日：2020-09-17

申请号：US16086275

申请日：2017-03-31

Applicant: Soitec

Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

IPC: H01L29/161 ,  H01L23/00

Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

公开(公告)号：US10672646B2

公开(公告)日：2020-06-02

申请号：US16301260

申请日：2017-05-17

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L27/12 ,  H01L21/762

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.

公开(公告)号：US09209301B1

公开(公告)日：2015-12-08

申请号：US14489841

申请日：2014-09-18

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Christophe Maleville

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/12 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L21/84

CPC classification number: H01L21/2253 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/76251 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/32 ,  H01L29/7849

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括提供包括基底基板，在基底基板上方的应变应力层，表面半导体层和应力层与表面半导体层之间的电介质层的绝缘体上半导体 。 离子被注入或穿过应力层的第一区域，并且在应力层的第一区域上方的表面半导体层上形成附加的半导体材料。 在应力层的第一区域上方的表面半导体层的第一区域中的应变状态被改变，并且沟槽结构至少部分地形成到基底衬底中。 在应力层的第二区域上方的表面半导体层的第二区域中改变应变状态。 使用这种方法制造半导体结构。

公开(公告)号：US12176244B2

公开(公告)日：2024-12-24

申请号：US17756431

申请日：2020-11-24

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Laurent Viravaux

IPC: H01L21/762 ,  H01L21/67

Abstract: A method for bonding a first substrate and a second substrate comprises bringing the first and second substrates into contact and implementing heating of a peripheral zone of at least one of the first and second substrates. The heating is initiated before the substrates are brought into contact and continued at least until the substrates are brought into contact in the zone. The heating is implemented by an infrared lamp configured to emit radiation having an outer boundary corresponding to the edge of the substrates.

公开(公告)号：US20230207382A1

公开(公告)日：2023-06-29

申请号：US17998833

申请日：2021-05-18

Applicant: Soitec

Inventor： Isabelle Bertrand ,  Walter Schwarzenbach ,  Frédéric Allibert

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: A method for fabricating a semiconductor-on-insulator substrate for radiofrequency applications, comprises:



forming a donor substrate through epitaxial growth of an undoped semiconductor layer on a p-doped semiconductor seed substrate;
forming an electrically insulating layer on the undoped epitaxial semiconductor,
implanting ion species through the electrically insulating layer, so as to form, in the undoped epitaxial semiconductor layer, a weakened area defining a semiconductor thin layer to be transferred,
providing a semiconductor carrier substrate having an electrical resistivity greater than or equal to 500 Ω·cm,
bonding the donor substrate to the carrier substrate via the electrically insulating layer, and
detaching the donor substrate along the weakened area of embrittlement so as to transfer the semiconductor thin layer from the donor substrate to the carrier substrate.

公开(公告)号：US20220157882A1

公开(公告)日：2022-05-19

申请号：US17649982

申请日：2022-02-04

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L21/762

Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 μm is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.

公开(公告)号：US11282889B2

公开(公告)日：2022-03-22

申请号：US16477499

申请日：2018-01-10

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L21/762

Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 μm is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.

公开(公告)号：US20220076992A1

公开(公告)日：2022-03-10

申请号：US17417715

申请日：2019-12-23

Applicant: Soitec

Inventor： Yvan Morandini ,  Walter Schwarzenbach ,  Frédéric Allibert ,  Eric Desbonnets ,  Bich-Yen Nguyen

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/322 ,  H01L27/12 ,  H01L29/06

Abstract: A semiconductor-on-insulator multilayer structure, comprises: —a stack, called the back stack, of the following layers from a back side to a front side of the structure: a semiconductor carrier substrate the electrical resistivity of which is between 500 Ω·cm and 30 kΩ·cm, a first electrically insulating layer, a first semiconductor layer, —at least one trench isolation that extends through the back stack at least down to the first electrically insulating layer), and that electrically isolates two adjacent regions of the multilayer structure, the multilayer structure being characterized in that it further comprises at least one FD-SOI first region, and at least one RF-SOI second region.

公开(公告)号：US20210366763A1

公开(公告)日：2021-11-25

申请号：US17444230

申请日：2021-08-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot

IPC: H01L21/762 ,  H01L27/146 ,  H01L31/028 ,  H01L21/02 ,  H01L21/203

Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.

公开(公告)号：US20210118936A1

公开(公告)日：2021-04-22

申请号：US17133316

申请日：2020-12-23

Applicant: Soitec

Inventor： Walter Schwarzenbach

IPC: H01L27/146 ,  H01L21/762

Abstract: A front-side type image sensor may include a substrate successively including: a P− type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.