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公开(公告)号：US12014084B2
公开(公告)日：2024-06-18
申请号：US17669085
申请日：2022-02-10
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Federico Goller , Dario Falanga , Michele Febbrarino , Massimo Montanaro
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0679
Abstract: A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.
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22.发明授权公开(公告)号：US11645004B2
公开(公告)日：2023-05-09
申请号：US17667087
申请日：2022-02-08
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A method for operating a differential memory includes: operating a main memory module differentially while executing a first program; copying first logic data from a first submodule of the main memory module to an auxiliary memory module; storing third logic data associated with a second program in a second submodule of the main memory module by overwriting second logic data associated with the first program, while maintaining the first logic data contained in the first submodule of the main memory module unaltered, where the second logic data are complementary to the first logic data; when a request for reading the first logic data is received during the storing of the third logic data in the second submodule of the main memory module, reading the first logic data from the auxiliary memory module; and executing the first or second programs by operating the main memory module in single-ended mode.
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23.发明授权公开(公告)号：US11380380B2
公开(公告)日：2022-07-05
申请号：US17088060
申请日：2020-11-03
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti , Guiseppe Scardino
Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.
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24.发明授权公开(公告)号：US11289158B2
公开(公告)日：2022-03-29
申请号：US17123518
申请日：2020-12-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
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25.发明申请公开(公告)号：US20210233582A1
公开(公告)日：2021-07-29
申请号：US17159381
申请日：2021-01-27
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20190214083A1
公开(公告)日：2019-07-11
申请号：US16225492
申请日：2018-12-19
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni
Abstract: In an embodiment, a method of accessing logic data stored in a differential memory using single-ended mode includes: storing second logic data in an auxiliary memory module of the differential memory by copying first logic data stored in a first main memory module of the differential memory into the auxiliary memory module; refreshing the first logic data; receiving a request for reading the first logic data; when refreshing the first logic data, fetching the second logic data when refreshing the first logic data in response to the request for reading the first logic data; and when not refreshing the first logic data, fetching the first logic data in response to the request for reading the first logic data.
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公开(公告)号：US10255973B2
公开(公告)日：2019-04-09
申请号：US15797732
申请日：2017-10-30
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Manfre , Cesare Torti , Fabio Enrico Carlo Disegni
Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.
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公开(公告)号：US10115470B2
公开(公告)日：2018-10-30
申请号：US15804790
申请日：2017-11-06
Applicant: STMicroelectronics S.r.l.
IPC: G11C16/28 , G11C16/08 , G05F3/24 , G11C5/14 , G11C16/30 , G11C7/14 , G11C16/10 , G11C16/14 , G11C16/24 , G11C7/12 , G11C7/04 , G11C8/10
Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
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29.发明申请公开(公告)号：US20180122470A1
公开(公告)日：2018-05-03
申请号：US15598962
申请日：2017-05-18
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2213/79 , G11C2213/82
Abstract: A non-volatile memory includes a number of bit lines, a number of source lines, and a number of memory cells of a non-volatile type. Each memory cell is coupled between a respective bit line and a respective source line. One or more discharge lines are coupled to a reference-voltage terminal. A number of controlled switches are coupled between a respective source line and a respective discharge line, which can be selectively driven for connecting the respective source line to the respective discharge line so as to form a conductive path between the respective source line and the reference-voltage terminal.
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公开(公告)号：US12260910B2
公开(公告)日：2025-03-25
申请号：US18148380
申请日：2022-12-29
Applicant: STMICROELECTRONICS S.r.l.
IPC: G11C13/00
Abstract: The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.
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