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公开(公告)号：US10115470B2
公开(公告)日：2018-10-30
申请号：US15804790
申请日：2017-11-06
Applicant: STMicroelectronics S.r.l.
IPC: G11C16/28 , G11C16/08 , G05F3/24 , G11C5/14 , G11C16/30 , G11C7/14 , G11C16/10 , G11C16/14 , G11C16/24 , G11C7/12 , G11C7/04 , G11C8/10
Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
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公开(公告)号：US20170221580A1
公开(公告)日：2017-08-03
申请号：US15484500
申请日：2017-04-11
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Francesco Perroni , Giuseppe Castagna
CPC classification number: G11C29/023 , G01R31/3187 , G06F11/2289 , G06F11/3037 , G06F11/3466 , G11C16/04 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C29/56012
Abstract: A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.
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公开(公告)号：US20130301348A1
公开(公告)日：2013-11-14
申请号：US13888593
申请日：2013-05-07
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Maurizio Francesco Perroni , Guido Desandre , Salvatore Polizzi , Giuseppe Castagna
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C8/10 , G11C13/0004 , G11C13/0069 , G11C2213/79
Abstract: A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.
Abstract translation: 用于相变非易失性存储器件的行解码器电路可以包括以字线布置的存储器单元。 该装置可以被配置为接收高于第一电源电压的第一电源电压和第二电源电压。 行解码器可以包括全局预解码级，其被配置为接收地址信号并且在第二电源电压的范围内产生高电压解码的地址信号，并且基于操作具有基于值的偏置信号。 行解码器可以包括耦合到全局预编码阶段的行解码器级。 行解码器级可以包括：选择驱动单元，被配置为基于高电压解码的地址信号产生块地址信号;以及行驱动单元，被配置为基于块地址生成用于偏置字线的行驱动信号 信号和偏置信号。
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4.发明申请公开(公告)号：US20170213580A1
公开(公告)日：2017-07-27
申请号：US15477695
申请日：2017-04-03
Applicant: STMicroelectronics S.r.l
Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.
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公开(公告)号：US08982612B2
公开(公告)日：2015-03-17
申请号：US13888593
申请日：2013-05-07
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Francesco Perroni , Guido Desandre , Salvatore Polizzi , Giuseppe Castagna
CPC classification number: G11C13/0028 , G11C8/10 , G11C13/0004 , G11C13/0069 , G11C2213/79
Abstract: A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.
Abstract translation: 用于相变非易失性存储器件的行解码器电路可以包括以字线布置的存储器单元。 该装置可以被配置为接收高于第一电源电压的第一电源电压和第二电源电压。 行解码器可以包括全局预解码级，其被配置为接收地址信号并且在第二电源电压的范围内产生高电压解码的地址信号，并且基于操作具有基于值的偏置信号。 行解码器可以包括耦合到全局预编码阶段的行解码器级。 行解码器级可以包括：选择驱动单元，被配置为基于高电压解码的地址信号产生块地址信号;以及行驱动单元，被配置为基于块地址生成用于偏置字线的行驱动信号 信号和偏置信号。
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Patent Agency Ranking
公开(公告)号：US10720223B2
公开(公告)日：2020-07-21
申请号：US15484500
申请日：2017-04-11
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Francesco Perroni , Giuseppe Castagna
IPC: G11C29/02 , G11C29/56 , G11C29/50 , G01R31/3187 , G06F11/22 , G06F11/30 , G06F11/34 , G11C16/04
Abstract: A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.
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公开(公告)号：US20180061499A1
公开(公告)日：2018-03-01
申请号：US15804790
申请日：2017-11-06
Applicant: STMicroelectronics S.r.l.
IPC: G11C16/28 , G11C5/14 , G11C16/24 , G11C16/14 , G11C16/10 , G11C16/30 , G05F3/24 , G11C7/14 , G11C7/12 , G11C16/08 , G11C7/04 , G11C8/10
CPC classification number: G11C16/28 , G05F3/245 , G11C5/147 , G11C7/04 , G11C7/12 , G11C7/14 , G11C8/10 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/30
Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
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公开(公告)号：US09830995B2
公开(公告)日：2017-11-28
申请号：US15140796
申请日：2016-04-28
Applicant: STMicroelectronics S.r.l.
IPC: G11C16/28 , G05F3/24 , G11C5/14 , G11C7/12 , G11C7/14 , G11C16/24 , G11C16/30 , G11C16/08 , G11C16/10 , G11C16/14 , G11C7/04 , G11C8/10
CPC classification number: G11C16/28 , G05F3/245 , G11C5/147 , G11C7/04 , G11C7/12 , G11C7/14 , G11C8/10 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/30
Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
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公开(公告)号：US20170062064A1
公开(公告)日：2017-03-02
申请号：US15140796
申请日：2016-04-28
Applicant: STMicroelectronics S.r.l
CPC classification number: G11C16/28 , G05F3/245 , G11C5/147 , G11C7/04 , G11C7/12 , G11C7/14 , G11C8/10 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/30
Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
Abstract translation: 用于偏置非易失性存储单元的电路包括全局偏置线和偏置节点之间的虚拟解码路径，耦合到虚拟解码路径并被配置为提供参考电流的参考电流发生器，被配置为设置单元 偏置节点上的偏置电压，以及补偿级，被配置为补偿偏置节点处的偏置级的电流吸收，使得参考电流将流过虚拟解码路径。
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10.发明授权公开(公告)号：US09239583B2
公开(公告)日：2016-01-19
申请号：US13899829
申请日：2013-05-22
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Giuseppe Castagna , MaurizioFrancesco Perroni
CPC classification number: G05F1/468 , G11C5/147 , G11C16/30 , G11C29/021
Abstract: A current-generator circuit is for generation of an output current of a value that is configurable as a function of a configuration signal. The circuit may have a first reference resistor element traversed by an intermediate current, the value of which is a function of a reference current, for supplying a first reference voltage. The circuit may also include a resistive divider stage receiving the configuration signal and supplying a second reference voltage as a function of the first reference voltage and of the configuration signal. A second reference resistor element supplies, as a function of the second reference voltage (Vref2), the output current on the output terminal. The value of resistance of the second reference resistor element may be matched to a respective value of resistance of the first reference resistor element.
Abstract translation: 电流发生器电路用于产生可配置为配置信号的函数的值的输出电流。 电路可以具有用于提供第一参考电压的中间电流穿过的第一参考电阻器元件，其中值为参考电流的函数。 电路还可以包括电阻分压器级，其接收配置信号并提供作为第一参考电压和配置信号的函数的第二参考电压。 第二参考电阻元件作为第二参考电压（Vref2）的函数提供输出端子上的输出电流。 第二参考电阻元件的电阻值可以与第一参考电阻元件的电阻的相应值相匹配。
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