公开(公告)号：US20160133736A1

公开(公告)日：2016-05-12

申请号：US14945936

申请日：2015-11-19

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  John Hongguang Zhang

IPC: H01L29/772 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7722 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/308 ,  H01L27/0225 ,  H01L27/14679 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66416

Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.

Abstract translation: 在掺杂有第一导电类型的碳化硅衬底上形成静电感应晶体管。 在碳化硅衬底的顶表面中的第一凹陷区域填充有原位掺杂有第二导电类型的外延生长栅极区域。 原位掺杂有第一导电类型的外延生长沟道区位于相邻的外延栅区之间。 原位掺杂有第一导电类型的外延生长的源极区位于外延沟道区上。 碳化硅衬底的底表面包括与沟道区垂直对准的第二凹陷区域并硅​​化以支持漏极接触的形成。 源区的顶表面被硅化以支持源接触的形成。 栅极引线外延生长并电耦合到栅极区域，栅极引线硅化以支持栅极接触的形成。

公开(公告)号：US10211257B2

公开(公告)日：2019-02-19

申请号：US15829397

申请日：2017-12-01

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars is stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

公开(公告)号：US20180350839A1

公开(公告)日：2018-12-06

申请号：US16050727

申请日：2018-07-31

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/1203 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02675 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/66628

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

公开(公告)号：US10103252B2

公开(公告)日：2018-10-16

申请号：US15361935

申请日：2016-11-28

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/085 ,  H01L29/66 ,  H01L27/098 ,  H01L29/78 ,  H01L29/808 ,  H01L29/417 ,  H01L29/10 ,  H01L21/283 ,  H01L29/06

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

公开(公告)号：US09865653B2

公开(公告)日：2018-01-09

申请号：US15293998

申请日：2016-10-14

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars ism stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

公开(公告)号：US09685456B2

公开(公告)日：2017-06-20

申请号：US14887814

申请日：2015-10-20

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02675 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/66628

Abstract: A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are then converted into a transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are converted into a transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

公开(公告)号：US20170077270A1

公开(公告)日：2017-03-16

申请号：US15361935

申请日：2016-11-28

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/66893 ,  H01L21/283 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66909 ,  H01L29/7832 ,  H01L29/8083

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Abstract translation: 垂直结型场效应晶体管（JFET）由包括掺杂有第一导电型掺杂剂的半导体衬底内的源极区域的半导体衬底支撑。 掺杂有第一导电型掺杂剂的半导体材料的鳍具有与源极区域接触的第一端，并且还包括第二端和第二端之间的侧壁。 漏极区域由从鳍片的第二端生长并掺杂有第一导电型掺杂剂的第一外延材料形成。 栅极结构由从鳍的侧壁生长并掺杂有第二导电型掺杂剂的第二外延材料形成。

公开(公告)号：US20170047349A1

公开(公告)日：2017-02-16

申请号：US15292465

申请日：2016-10-13

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/417

CPC classification number: H01L27/1211 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/845 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

Abstract translation: 晶体管包括由衬底支撑并具有源极区，沟道区和漏极区的有源区。 栅极堆叠在沟道区域上方延伸，并且第一侧壁围绕栅极堆叠。 分别在与第一侧壁相邻的有源区域的源极和漏极区域之上提供凸起的源极区域和凸起的漏极区域。 第二侧壁周向地围绕凸起的源极区域和升高的漏极区域中的每一个。 第二侧壁延伸在凸起源区域的顶表面上方，并且凸起的漏极区域限定由第一和第二侧壁横向限定的区域。 导电材料填充区域以分别形成源极接触和漏极接触到升高的源极区域和升高的漏极区域。

公开(公告)号：US20170033284A1

公开(公告)日：2017-02-02

申请号：US15293998

申请日：2016-10-14

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L45/00 ,  H01L23/528 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars ism stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

Abstract translation: 存储单元包括衬底层，多个硅化半导体鳍片堆叠在衬底层上并彼此间隔开。 第一金属衬垫层堆叠在多个硅化半导体鳍片上和衬底层上。 在第一金属衬垫层上堆叠多个第一接触柱，与多个硅化半导体鳍片中的不同的一个相邻。 可配置的电阻结构覆盖层叠在基板层上的第一金属衬垫层的部分和堆叠在多个硅化半导体鳍片中的每一个上的第一金属衬垫层的部分。 金属填充层堆叠在可配置电阻结构上。 多个第二接触柱堆叠在金属填充层上，与多个相邻的相邻硅化物半导体散热片之间的空间相邻。

公开(公告)号：US09543304B2

公开(公告)日：2017-01-10

申请号：US14677404

申请日：2015-04-02

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L29/66 ,  H01L27/085 ,  H01L27/098 ,  H01L29/78 ,  H01L29/808 ,  H01L29/417 ,  H01L29/10 ,  H01L21/283

CPC classification number: H01L29/66893 ,  H01L21/283 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66909 ,  H01L29/7832 ,  H01L29/8083

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Abstract translation: 垂直结型场效应晶体管（JFET）由包括掺杂有第一导电型掺杂剂的半导体衬底内的源极区域的半导体衬底支撑。 掺杂有第一导电型掺杂剂的半导体材料的鳍具有与源极区域接触的第一端，并且还包括第二端和第二端之间的侧壁。 漏极区域由从鳍片的第二端生长并掺杂有第一导电型掺杂剂的第一外延材料形成。 栅极结构由从鳍的侧壁生长并掺杂有第二导电型掺杂剂的第二外延材料形成。