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公开(公告)号：US20170363507A1
公开(公告)日：2017-12-21
申请号：US15694156
申请日：2017-09-01
Applicant: STMicroelectronics (Crolles 2) SAS , STMICROELECTRONICS SA
Inventor： Jean-Francois Carpentier , Patrick Le Maitre , Jean-Robert Manouvrier , Charles Baudot , Bertrand Borot
CPC classification number: G01M11/02 , G01M11/33 , G01R31/2656 , G01R31/27 , G01R31/2884 , G01R31/303 , G01R31/311 , G01R31/31728 , G01R35/00 , G02B6/00 , G02B6/12004 , G02B6/2808 , G02B6/34
Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.
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公开(公告)号：US11680870B2
公开(公告)日：2023-06-20
申请号：US17516165
申请日：2021-11-01
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Philippe Grosse , Patrick Le Maitre , Jean-Francois Carpentier
IPC: G01M11/02 , G02B6/28 , G02B6/34 , G02B6/12 , G02B6/00 , G01M11/00 , G01R31/265 , G01R31/27 , G01R31/28 , G01R31/303 , G01R31/311 , G01R31/317 , G01R35/00
CPC classification number: G01M11/02 , G01M11/33 , G01R31/2656 , G01R31/27 , G01R31/2884 , G01R31/303 , G01R31/311 , G01R31/31728 , G01R35/00 , G02B6/00 , G02B6/12004 , G02B6/2808 , G02B6/34
Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.
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公开(公告)号：US11555852B2
公开(公告)日：2023-01-17
申请号：US16249546
申请日：2019-01-16
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Patrick Le Maitre , Jean-Francois Carpentier
Abstract: An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.
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公开(公告)号：US20190250213A1
公开(公告)日：2019-08-15
申请号：US16249546
申请日：2019-01-16
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Patrick Le Maitre , Jean-Francois Carpentier
IPC: G01R31/317 , H01L25/16 , G02B6/28 , G02F1/21
CPC classification number: G01R31/31728 , G01M11/3127 , G01M11/3145 , G02B6/12004 , G02B6/12011 , G02B6/12019 , G02B6/12033 , G02B6/2773 , G02B6/2813 , G02B6/29332 , G02B2006/12147 , G02F1/21 , G02F2001/217 , H01L25/167 , H01S5/0268
Abstract: An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.
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公开(公告)号：US20180341061A1
公开(公告)日：2018-11-29
申请号：US15607153
申请日：2017-05-26
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Jean-Francois Carpentier , Patrick Le Maitre
IPC: G02B6/12 , G02B6/122 , G01R31/308
Abstract: A power balancing device includes first, second, and third power splitting devices on a semiconductor substrate. The first power splitting device includes an input, a first output, and a second output. A ratio of the power outputs at the first and second outputs is a first ratio. The second power splitting device includes third and fourth outputs and an input coupled to the first output. A ratio of the power outputs at the third and fourth outputs is a second ratio. The third power splitting device includes a fifth and sixth output and an input coupled to the second output. A ratio of the power outputs at the fifth and sixth outputs is a third ratio. The first, second, and third ratios are substantially similar. The input of the first power splitting device and the third and sixth outputs make the input and outputs respectively of the power balancing device.
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Patent Agency Ranking
公开(公告)号：US20170307687A1
公开(公告)日：2017-10-26
申请号：US15489127
申请日：2017-04-17
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Philippe Grosse , Patrick Le Maitre , Jean-Francois Carpentier
IPC: G01R31/317 , G01R31/27 , G01R31/311 , G01R31/28 , G01R31/303 , G01R35/00 , G01R31/265
CPC classification number: G01M11/02 , G01M11/33 , G01R31/2656 , G01R31/27 , G01R31/2884 , G01R31/303 , G01R31/311 , G01R31/31728 , G01R35/00 , G02B6/00 , G02B6/12004 , G02B6/2808 , G02B6/34
Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.
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27.发明申请公开(公告)号：US20170288781A1
公开(公告)日：2017-10-05
申请号：US15083616
申请日：2016-03-29
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
Inventor： Jean-Francois Carpentier , Patrick Lemaitre , Jean-Robert Manouvrier , Denis Pache , Stephane Le Tual
IPC: H04B10/516 , H04L25/49
CPC classification number: H04B10/541 , G02F1/0121 , G02F1/2257 , H04B10/505 , H04L25/4917
Abstract: An optical modulator includes an optical waveguide including at least a first PN junction phase shifter and a second PN junction phase shifter. A driver circuit drives operation of the first and second PN junction phase shifters in response to a pulse amplitude modulated (PAM) analog signal having 2n levels. The PAM analog signal is generated by a digital to analog converter that receives an n-bit input signal. In an implementation, the optical waveguide and PN junction phase shifters are formed on a first integrated circuit chip and the driver circuit is formed on a second integrated circuit chip that is stacked on and electrically connected to the first integrated circuit chip.
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公开(公告)号：US09709739B1
公开(公告)日：2017-07-18
申请号：US15450150
申请日：2017-03-06
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Jean-Francois Carpentier , Patrick Le Maitre , Bertrand Borot
CPC classification number: G02B6/125 , G02B6/02042 , G02B6/12004 , G02B6/30 , G02B6/4249 , G02B6/43 , G02B2006/12142 , G02B2006/12147
Abstract: A coupling module includes optical couplers that are coupled to waveguides. The optical couplers are configured to couple to cores of a multi-core optical fiber. The waveguides each include an external part extending from the module and an internal part extending into the module for connecting the external part to the associated optical coupler. The external part of some of the waveguides extends in a preferential direction, while the external part of others of the waveguides extends in a direction opposite to the preferential direction. The internal parts may include a curved portion configured for forming a turn-back.
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公开(公告)号：US20170003571A1
公开(公告)日：2017-01-05
申请号：US15068704
申请日：2016-03-14
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
Inventor： Jean-Francois Carpentier , Patrick LeMaitre , Denis Pache
CPC classification number: G02F1/2255 , G02F1/0123 , G02F1/025 , G02F1/2257 , G02F2001/212
Abstract: An integrated modulator of the Mach-Zehnder type includes two optical arms containing waveguides with PN junctions and biasing circuits for reverse biasing the PN junctions in response to a control signal. The two optical arms are situated within a semiconductor substrate of a first element that also has an interconnection region. The biasing circuits are situated, in part, within a substrate of a second element that also contains an interconnection region. The first and second elements are rigidly attached to each other via their respective interconnection regions.
Abstract translation: Mach-Zehnder型集成调制器包括两个含有PN结的波导的光学臂和用于响应控制信号反向偏置PN结的偏置电路。 两个光学臂位于也具有互连区域的第一元件的半导体衬底内。 偏置电路部分地位于也包含互连区域的第二元件的衬底内。 第一和第二元件通过其相应的互连区域彼此刚性连接。
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公开(公告)号：US20140075726A1
公开(公告)日：2014-03-20
申请号：US14084394
申请日：2013-11-19
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
Inventor： David Petit , Sylvain Joblot , Pierre Bar , Jean-Francois Carpentier , Pierre Dautriche
IPC: H03H3/02
CPC classification number: H03H3/02 , G01N29/022 , G02F1/133707 , H03H3/04 , H03H9/0028 , H03H9/02102 , H03H9/175 , Y10T29/42 , Y10T29/49005 , Y10T29/49155
Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.
Abstract translation: 一种制造晶片的方法，其上形成有谐振器，每个谐振器包括在半导体衬底上方的一叠层，其从衬底表面依次包括：布拉格反射镜; 由具有与所有其它堆叠层相反的符号的声速的温度系数的材料制成的补偿层; 和压电谐振器，该方法包括以下连续步骤：a）沉积补偿层; 和b）由于沉积方法而减小补偿层的厚度不等式，使得该层在每个谐振器的电平上具有相同的厚度，优于2％以内，优选在1％以内。
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