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公开(公告)号：US20140095932A1
公开(公告)日：2014-04-03
申请号：US14038501
申请日：2013-09-26
Inventor： Daniele Mangano , Ignazio Antonino Urzi
IPC: G06F11/27
CPC classification number: G06F11/27 , G06F11/2236 , G06F11/3648
Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.
Abstract translation: 系统包括处理器和通过互连网络连接的多个电路，其中与每个电路相关联的是相应的通信接口，被配置为在相应电路和互连网络之间交换数据。 特别地，调试单元与每个通信接口相关联。 每个调试单元可配置为数据插入点，其中调试单元通过相应的通信接口将数据发送到互连网络，或者每个调试单元可配置为数据接收点，其中调试单元通过 来自互连网络的相应通信接口的装置。
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公开(公告)号：US20210357015A1
公开(公告)日：2021-11-18
申请号：US16874020
申请日：2020-05-14
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Michele Alessandro Carrano , Pasquale Butta' , Sergio Abenda
IPC: G06F1/3234 , H03K3/037
Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.
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公开(公告)号：US10859617B2
公开(公告)日：2020-12-08
申请号：US16136121
申请日：2018-09-19
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Riccardo Condorelli , Daniele Mangano
Abstract: In one embodiment, an inductive/LC sensor device includes: an energy storage device for accumulating excitation energy, an LC sensor configured to oscillate using energy accumulated in the energy storage device and transferred to the LC sensor, an energy detector for detecting the energy accumulated in the energy storage device reaching a charge threshold, and at least one switch coupled with the energy detector for terminating accumulating excitation energy in the energy storage device when the charge threshold is detected having been reached by the energy detector.
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公开(公告)号：US10579561B2
公开(公告)日：2020-03-03
申请号：US15940650
申请日：2018-03-29
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Daniele Mangano , Mirko Dondini , Salvatore Pisasale
Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. When the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, when the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
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公开(公告)号：US10236066B2
公开(公告)日：2019-03-19
申请号：US15692158
申请日：2017-08-31
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Michele Alessandro Carrano , Gaetano Di Stefano , Roberto Sebastiano Ruggirello
IPC: G11C16/10 , G11C8/20 , G11C13/00 , G06F12/02 , G06F12/0868
Abstract: A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.
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Patent Agency Ranking
公开(公告)号：US10082824B2
公开(公告)日：2018-09-25
申请号：US14965002
申请日：2015-12-10
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Daniele Mangano , Riccardo Condorelli
CPC classification number: G06F1/12 , G06F1/14 , G06F1/3243 , H03L1/00 , Y02D10/152
Abstract: A clock generator includes a microcontroller unit calibrated by aligning at subsequent calibration times a frequency of a first clock with respect to the frequency of a second clock having a higher frequency accuracy than the first clock, with the frequency of the first clock varying between subsequent calibration times. The frequency of the first clock is aligned to a frequency which is offset by a certain amount with respect to the frequency of the second clock to counter frequency error which may accumulate over time due to the variation in the frequency of the first clock.
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公开(公告)号：US09897630B2
公开(公告)日：2018-02-20
申请号：US14751254
申请日：2015-06-26
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Riccardo Condorelli , Daniele Mangano
Abstract: A method of interfacing an LC sensor with a control unit is described. The control unit may include first and second contacts, and the LC sensor may be connected between the first and second contacts. The method may include starting the oscillation of the LC sensor, and monitoring the voltage at the second contact, in which the voltage at the second contact corresponds to the sum of the voltage at the first contact and the voltage at the LC sensor. The voltage at the first contact may be varied such that the voltage at the second contact does not exceed an upper voltage threshold and does not fall below a lower voltage threshold.
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公开(公告)号：US09692672B2
公开(公告)日：2017-06-27
申请号：US14604439
申请日：2015-01-23
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Salvatore Pisasale
CPC classification number: H04L43/0858 , G06F1/04 , G06F13/4291 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/10
Abstract: A communication system for interfacing a transmitting circuit with a receiving circuit includes a transmission interface for receiving data from the transmitting circuit and transmitting the data received over at least one data line in response to a transmission clock signal. The communication system also includes a reception interface configured for receiving the data in response to a reception clock signal and transmitting the data received to the receiving circuit. In particular, the system is configured for generating a plurality of clock signals that have the same frequency but are phase-shifted with respect to one another. In addition, during a calibration phase, the system is configured for selecting one of the clock signals for the transmission clock signal or reception clock signal via selecting at least one of the clock signals for transmission of test signals via the transmission interface and verifying whether the test signals received via the reception interface are correct. The system is further configured to use, during normal operation, the clock signal selected during the calibration phase for transmission of data.
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公开(公告)号：US09191033B2
公开(公告)日：2015-11-17
申请号：US13854419
申请日：2013-04-01
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Salvatore Pisasale , Carmelo Pistritto
CPC classification number: H03M13/6522 , G06F13/4286 , H03M13/51
Abstract: A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.
Abstract translation: 一种完成检测器电路，用于检测在根据延迟不敏感编码（例如，双轨，m-of-n，Berger编码）组织的信号线在通信信道上完成异步数据的传输，包括：用于 检测上述信号线上的数据，其配置用于：i）产生指示信号线上的异步数据是稳定的事实的第一信号; ii）产生指示信号线被断言的事实的第二信号; 以及提供有第一信号和第二信号的异步有限状态机，用于产生检测异步数据传输完成的信号，检测信号具有：第一值，当第一信号被断言时; 以及第二值，当所述第二信号被断言时; 并且当所述第一信号和所述第二信号的一个或另一个被断言时，它们处于保持状态。
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公开(公告)号：US08990436B2
公开(公告)日：2015-03-24
申请号：US13904379
申请日：2013-05-29
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Salvatore Pisasale , Mirko Dondini
CPC classification number: G06F9/466 , G06F13/1626 , G06F2213/0038
Abstract: In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.
Abstract translation: 在一个实施例中，通过分配经过一致性检查的事务标识符来管理诸如片上系统（SoC）的系统的至少一个模块到诸如存储器的多个目标模块之一的访问事务。 如果已经为相同的给定目标模块发出了支票的输入标识符，则向相关标识符/给定目标模块对发送相同的输入标识符作为一致的输出标识符。 相反，如果相对于所述检查的所述输入标识符尚未被发布或者已经针对与所考虑的目标模块不同的目标模块已经被发布到相关标识符/给定目标模块对，则与输入标识符不同的新标识符 ，被分配为一致的输出标识符。
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