公开(公告)号：US10237725B2

公开(公告)日：2019-03-19

申请号：US15729852

申请日：2017-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： Ranieri Guerra ,  Roberto Larosa ,  Giuseppe Palmisano

IPC: H04B1/16 ,  H04B17/318 ,  H03D1/22 ,  H04W8/22 ,  H04W52/02

Abstract: A receiver for digital signals includes a radiofrequency stage. A feedback loop controls a variable attenuation resistance applied to a modulated radiofrequency signal passing through the radiofrequency stage as a function of a comparison of an amplitude of the modulated radiofrequency signal with a reference value. A baseband stage includes an RC network cascaded to the radiofrequency stage and coupled to a baseband detector that generates the baseband signal. The feedback loop includes a circuit for detecting a range of variation of the comparison. The value of the variable resistance is controlled as a function of an end value (e.g., maximum or minimum) of the detected range of variation.

公开(公告)号：US20170288568A1

公开(公告)日：2017-10-05

申请号：US15359213

申请日：2016-11-22

Applicant: STMicroelectronics S.r.l.

Inventor： Leandro Grasso ,  Ranieri Guerra ,  Giuseppe Palmisano

IPC: H02M7/217

CPC classification number: H02M7/217 ,  H02M7/219

Abstract: A rectifier cell includes a first cell branch and a second cell branch that extend in parallel between two opposite nodes receiving an a.c. signal. The first cell branch includes a first pair of transistors arranged with their current paths cascaded, with a first intermediate point in-between. The second cell branch includes a second pair of transistors arranged with their current paths cascaded, with a second intermediate point in-between. Each of the pairs of transistors includes a first transistor with a control terminal coupled to one of the two opposite nodes and a second transistor with a control terminal coupled to the other of the two opposite nodes. The bulks of the transistors receive voltages in order to vary the transistor threshold voltage by bringing the threshold voltage to a first value during forward conduction and to a second value during reverse conduction.

公开(公告)号：US20170154727A1

公开(公告)日：2017-06-01

申请号：US15163430

申请日：2016-05-24

Applicant: STMicroelectronics S.r.l.

Inventor： Nunzio Spina ,  Egidio Ragonese ,  Giuseppe Palmisano ,  Nunzio Greco

IPC: H01F38/14 ,  H04B5/00 ,  H03B15/00 ,  H02M7/06 ,  H02J50/12

CPC classification number: H01F38/14 ,  H01F2038/143 ,  H01F2038/146 ,  H01L23/66 ,  H01L24/06 ,  H02J50/12 ,  H02M7/06 ,  H03B15/00 ,  H04B5/0037 ,  H04L25/0266

Abstract: A galvanic isolation system includes a first isolation barrier and a second isolation barrier. The first isolation barrier includes a transformer. The second isolation barrier includes an inductive circuit connected to a secondary winding of the transformer. The first and the second isolation barriers are coupled to form an LC resonant network.

公开(公告)号：US09479208B2

公开(公告)日：2016-10-25

申请号：US14751470

申请日：2015-06-26

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Giuseppe Papotto ,  Giuseppe Palmisano

IPC: H03C3/00 ,  H03M3/00 ,  H04B1/16 ,  H04W56/00 ,  H04L27/36 ,  H03F3/24 ,  H03K5/156

CPC classification number: H04B1/16 ,  H03F3/24 ,  H03K5/1565 ,  H04L27/364 ,  H04W56/0035 ,  H04W56/005

Abstract: A system for correction of the phase error in in-phase and quadrature signals may include a first signal and a second signal. The system includes a first circuit and a second circuit, each circuit configured for receiving a square-wave input signal and supplying a respective square-wave output signal. The output signal is delayed with respect to the input signal and each circuit is configured in such a way that the propagation delay of a rising edge and the propagation delay of a falling edge between the input signal and the output signal are configurable. The first circuit is configured for receiving the first signal, and the second circuit is configured for receiving the second signal.

Abstract translation: 用于校正同相和正交信号中的相位误差的系统可以包括第一信号和第二信号。 该系统包括第一电路和第二电路，每个电路被配置为接收方波输入信号并提供相应的方波输出信号。 输出信号相对于输入信号被延迟，并且每个电路被配置成使得输入信号和输出信号之间的上升沿的传播延迟和下降沿的传播延迟是可配置的。 第一电路被配置为接收第一信号，并且第二电路被配置为接收第二信号。

公开(公告)号：US09306614B2

公开(公告)日：2016-04-05

申请号：US14631397

申请日：2015-02-25

Applicant: STMicroelectronics S.r.l.

Inventor： Egidio Ragonese ,  Vincenzo Fiore ,  Nunzio Spina ,  Pierpaolo Lombardo ,  Giuseppe Palmisano

IPC: H04B1/40 ,  H04L27/08 ,  H03B5/12 ,  G08C19/16 ,  G08C19/02 ,  H04B3/54

CPC classification number: H04B1/40 ,  G08C19/02 ,  G08C19/16 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1296 ,  H03B2200/0074 ,  H04B3/54 ,  H04L27/08

Abstract: An apparatus includes first and second oscillator circuits. A transformer has a primary winding coupling the first oscillator circuit to the second oscillator circuit and a secondary winding. A first outgoing communications circuit is coupled to the second oscillator circuit and drives an amplitude modulated data signal thereto. A first incoming communications circuit is coupled to the primary winding of the transformer. A second outgoing communications circuit is coupled to the secondary winding drives an amplitude modulated data signal thereto. A second incoming communications circuit is coupled to the secondary winding. The secondary winding is magnetically coupled with the primary winding so the secondary winding receives an output power and an incoming data transmission based upon the amplitude modulated data signal, and so the primary winding receives an incoming high speed data transmission based upon the amplitude modulated data signal.

Abstract translation: 一种装置包括第一和第二振荡器电路。 变压器具有将第一振荡器电路耦合到第二振荡器电路的初级绕组和次级绕组。 第一输出通信电路耦合到第二振荡器电路并向其驱动调幅数据信号。 第一输入通信电路耦合到变压器的初级绕组。 耦合到次级绕组的第二输出通信电路驱动其幅度调制数据信号。 第二输入通信电路耦合到次级绕组。 次级绕组与初级绕组磁耦合，使得次级绕组基于幅度调制数据信号接收输出功率和输入数据传输，因此初级绕组基于幅度调制数据信号接收输入的高速数据传输 。

公开(公告)号：US12210089B2

公开(公告)日：2025-01-28

申请号：US18418298

申请日：2024-01-21

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Parisi ,  Andrea Cavarra ,  Alessandro Finocchiaro ,  Giuseppe Papotto ,  Giuseppe Palmisano

IPC: G01S13/58 ,  G01S7/40 ,  G01S13/931 ,  H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H03L7/193

Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·Δf, where M is an integer from 0 to N−1, where N is a number of intervals into which a frequency range for the output signal is divided, and where Δf is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.

公开(公告)号：US20230179244A1

公开(公告)日：2023-06-08

申请号：US17457496

申请日：2021-12-03

Applicant: STMicroelectronics S.r.l.

Inventor： Nunzio Spina ,  Giuseppe Palmisano ,  Alessandro Castorina

IPC: H04B1/16 ,  H03F3/19 ,  H04L27/06

CPC classification number: H04B1/16 ,  H03F3/19 ,  H04L27/06 ,  H03F2200/451

Abstract: A method for calibrating the DC operating point of a PWM receiver circuit is disclosed. The PWM receiving circuit includes an envelop detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between a supply voltage and a reference voltage and functions as a voltage divider. Each switch, when closed, accesses a second voltage at a node of the second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches is closed one at a time, and the second voltage is compared with a first voltage at a first node of the first resistor string. The switch that, when closed, produces the smallest difference between the first voltage and the second voltage remains closed after the calibration process, and is used for demodulating the PWM signal.

公开(公告)号：US20230018212A1

公开(公告)日：2023-01-19

申请号：US17838159

申请日：2022-06-10

Applicant: STMicroelectronics S.r.l.

Inventor： Giuseppe Papotto ,  Andrea Cavarra ,  Giuseppe Palmisano

IPC: H03K5/00 ,  H03F3/20 ,  G01S13/931

Abstract: In an embodiment a circuit includes frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value and a transformer including a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground.

公开(公告)号：US11537153B2

公开(公告)日：2022-12-27

申请号：US16459169

申请日：2019-07-01

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Orazio Cavallaro ,  Germano Nicollini ,  Giuseppe Palmisano

IPC: G05F1/46 ,  G05F1/59 ,  G05F1/575 ,  G05F3/24 ,  G05F3/30

Abstract: A voltage reference circuit includes a first circuit block configured to generate a proportional to absolute temperature current, the first circuit block comprising a current mirror amplifier, a second circuit block coupled to the first circuit block and configured to generated a complimentary to absolute temperature current, and a third circuit block coupled to both the first circuit block and the second circuit block. The second circuit block includes a multi-stage common-source amplifier. The third circuit block is configured to combine the proportional to absolute temperature current and the complimentary to absolute temperature current to generate a reference voltage at an output of the voltage reference circuit.

公开(公告)号：US10044290B2

公开(公告)日：2018-08-07

申请号：US15160674

申请日：2016-05-20

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Finocchiaro ,  Giuseppe Palmisano

IPC: H01F27/42 ,  H02M7/25 ,  H02M3/07 ,  H02M7/217

Abstract: An energy harvester circuit operates to harvest energy in battery-less electrical apparatus. The circuit includes a string of capacitors coupled to a circuit input to receive energy to be harvested. A string of transistors are coupled as pumping transistors to respective ones of the capacitors in the string of capacitors. A compensation coupling circuit is coupled between each transistor in the string of pumping transistors and one of a subsequent or a preceding transistor in the string of pumping transistors.