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21.发明授权公开(公告)号：US11322201B2
公开(公告)日：2022-05-03
申请号：US17159381
申请日：2021-01-27
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.
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22.发明申请公开(公告)号：US20210166745A1
公开(公告)日：2021-06-03
申请号：US17088060
申请日：2020-11-03
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti , Guiseppe Scardino
Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.
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公开(公告)号：US10861543B2
公开(公告)日：2020-12-08
申请号：US16804698
申请日：2020-02-28
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré
Abstract: In one embodiment, a memory device includes a first sense amplifier, a second sense amplifier, a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier, a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier, a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier, a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier, a third lower switch arranged between a second lower main bit line to a second input of the first sense amplifier, and a third upper switch arranged between a second upper main bit line to a second input of the second sense amplifier.
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公开(公告)号：US10658032B2
公开(公告)日：2020-05-19
申请号：US16155659
申请日：2018-10-09
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfré , Massimo Fidone
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
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公开(公告)号：US10600479B2
公开(公告)日：2020-03-24
申请号：US16227438
申请日：2018-12-20
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré
Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.
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Patent Agency Ranking
公开(公告)号：US11798630B2
公开(公告)日：2023-10-24
申请号：US17407903
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella Carissimi , Fabio Enrico Carlo Disegni , Chantal Auricchio , Cesare Torti , Davide Manfre' , Laura Capecchi , Emanuela Calvetti , Stefano Zanchi
CPC classification number: G11C16/102 , G11C7/04 , G11C16/24 , G11C16/28 , G11C16/30
Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.
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27.发明授权公开(公告)号：US11756614B2
公开(公告)日：2023-09-12
申请号：US17657861
申请日：2022-04-04
Applicant: STMicroelectronics S.r.l.
CPC classification number: G11C13/0004 , G11C7/02 , G11C7/06 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0069
Abstract: A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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28.发明授权公开(公告)号：US11328768B2
公开(公告)日：2022-05-10
申请号：US17119979
申请日：2020-12-11
Applicant: STMicroelectronics S.r.l.
Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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公开(公告)号：US11049561B2
公开(公告)日：2021-06-29
申请号：US16903264
申请日：2020-06-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Federico Goller , Cesare Torti , Marcella Carissimi , Emanuela Calvetti
Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.
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30.发明申请公开(公告)号：US20210193220A1
公开(公告)日：2021-06-24
申请号：US17119979
申请日：2020-12-11
Applicant: STMicroelectronics S.r.l.
Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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