公开(公告)号：US11973142B2

公开(公告)日：2024-04-30

申请号：US17888649

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook Kim ,  Yunseong Lee ,  Sanghyun Jo ,  Jinseong Heo

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L21/28185 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.

公开(公告)号：US11824119B2

公开(公告)日：2023-11-21

申请号：US18060372

申请日：2022-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong Heo ,  Sangwook Kim ,  Yunseong Lee ,  Sanghyun Jo

IPC: H01L29/78 ,  H01L21/28 ,  G11C11/22 ,  H01L29/66

CPC classification number: H01L29/78391 ,  G11C11/223 ,  H01L29/40111 ,  H01L29/6684

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

公开(公告)号：US20230307553A1

公开(公告)日：2023-09-28

申请号：US18324638

申请日：2023-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong Heo ,  Taehwan Moon ,  Hagyoul Bae ,  Seunggeol Nam ,  Sangwook Kim ,  Kwanghee Lee

IPC: H01L29/86 ,  H10K10/50 ,  H10K19/00 ,  H10B69/00

CPC classification number: H01L29/86 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201 ,  H10B69/00

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US11677025B2

公开(公告)日：2023-06-13

申请号：US17513050

申请日：2021-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong Lee ,  Jinseong Heo ,  Sangwook Kim ,  Sanghyun Jo

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/28 ,  H10B51/30 ,  H01L27/1159

CPC classification number: H01L29/78391 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02175 ,  H01L29/0847 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684 ,  H01L21/02181 ,  H01L21/02189 ,  H01L27/1159

Abstract: An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.

公开(公告)号：US11640980B2

公开(公告)日：2023-05-02

申请号：US17399175

申请日：2021-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee Lee ,  Sangwook Kim

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/24

Abstract: A field-effect transistor includes a gate structure comprising a structure in which a first insulating layer, a first gate electrode, and a second insulating layer are sequentially stacked on a first conductive layer, the gate structure surrounding a first hole through the first insulating layer and exposing a part of the first conductive layer; a second conductive layer on the second insulating layer and surrounding a second hole connected to the first hole and exposing a part of the first conductive layer; a first gate insulating layer covering an inner wall of the gate structure exposed by the first hole; a semiconductor layer covering a part of the first conductive layer exposed through the first hole and the second hole, the first gate insulating layer, and the second conductive layer; a second gate insulating layer covering the semiconductor layer; and a second gate electrode filling the first and second holes.

公开(公告)号：US11600712B2

公开(公告)日：2023-03-07

申请号：US16691772

申请日：2019-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Jo ,  Sangwook Kim ,  Yunseong Lee ,  Jinseong Heo

IPC: H01L29/51 ,  H01L27/06 ,  H01L49/02

Abstract: A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.

公开(公告)号：US11294290B2

公开(公告)日：2022-04-05

申请号：US16911819

申请日：2020-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo-Yong Cho ,  Sangwook Kim ,  Jaewon Yang

IPC: G03F7/20 ,  H01L21/308 ,  H01L21/027

Abstract: Disclosed are reticle fabrication methods and semiconductor device fabrication methods. The reticle fabrication method includes performing a photolithography process on a test substrate using a first reticle having first patterns, measuring the test substrate to obtain measured images, designing a second reticle having second patterns, redesigning the second reticle based on a margin of the photolithography process, and manufacturing the redesigned second reticle. Redesigning the second reticle includes obtaining sample images from the measured images when the first patterns are the same as the second patterns, obtaining contour images that have contours of sample patterns in the sample images, overlapping the contours to obtain a contour overlay value, and comparing the contour overlay value with a reference value to determine defects of the second patterns.

公开(公告)号：US20170134914A1

公开(公告)日：2017-05-11

申请号：US15344464

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

Inventor： Yong-Seok Park ,  Soo-Young Jang ,  Daedong Park ,  Seongsoo Hong ,  Sangwook Kim

IPC: H04W4/12 ,  H04W76/02

Abstract: A method for transmitting data in a mobile device includes transmitting, to a reception device, a connection request message comprising information indicating whether the transmission device supports message transmission having temporal correlation; receiving, from the reception device, a connection response message comprising information indicating whether the reception device supports the message transmission in response to the connection request message; and if both the transmission device and the reception device support the message transmission, transmitting, to the reception device, at least two of messages having temporal correlation, the at least two of messages comprising identification information, wherein the identification information indicates that the at least two of messages have temporal correlation.

公开(公告)号：US12230711B2

公开(公告)日：2025-02-18

申请号：US18487275

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong Heo ,  Sangwook Kim ,  Yunseong Lee ,  Sanghyun Jo ,  Hyangsook Lee

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/78

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

公开(公告)号：US20240362395A1

公开(公告)日：2024-10-31

申请号：US18394330

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangwoo Heo ,  Bayram Yenikaya ,  Xin Li ,  Sangwook Kim

IPC: G06F30/398 ,  G03F1/36

CPC classification number: G06F30/398 ,  G03F1/36

Abstract: A layout correction method for a semiconductor device includes receiving a design layout including at least a target layer and a reference layer, detecting target edges including target patterns in the target layer, and detecting reference edges including reference patterns in the reference layer, determining a dissection point in a section intersecting a space between reference patterns on a target edge having three or more intersecting reference edges, generating segments by dissecting the target edges based on dissection points set for the target edges, setting an evaluation point at an intermediate point of a section intersecting a reference pattern in a segment intersecting the reference pattern, among the segments, determining a movement amount of segments having evaluation points set on the segments by inputting a feature measured at the evaluation points to a layout correction model, and generating a corrected layout by moving the segments based on the movement amount.