公开(公告)号：US10991825B2

公开(公告)日：2021-04-27

申请号：US16167815

申请日：2018-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Jong Chui Park ,  Kye Hyun Baek

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom. The plurality of fins includes a plurality of active fins and at least one non-active fin disposed between ones of the plurality of active fins. The device also includes at least one gate electrode crossing at least a portion of the active fins. The device further includes a plurality of source/drain regions disposed on the active fins adjacent the at least one gate electrode and separated from one another by the at least one non-active fin.

公开(公告)号：US10797051B2

公开(公告)日：2020-10-06

申请号：US16716384

申请日：2019-12-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonjae Kim ,  Cheol Kim ,  Yong-Hoon Son ,  Jin-Hyuk Yoo ,  Woojin Jung

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L21/768 ,  H01L21/306 ,  H01L21/311 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/165

Abstract: A semiconductor device includes a substrate having an active pattern, a conductive pattern crossing the active pattern, a spacer structure on at least one side surface of the conductive pattern, and a capping structure on the conductive pattern. The capping structure includes a first capping pattern and a second capping pattern. The second capping pattern is disposed on a top surface of the first capping pattern and a top surface of the spacer structure.

公开(公告)号：US20190288114A1

公开(公告)日：2019-09-19

申请号：US16167815

申请日：2018-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Jong Chul Park ,  Kye Hyun Baek

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08

Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom. The plurality of fins includes a plurality of active fins and at least one non-active fin disposed between ones of the plurality of active fins. The device also includes at least one gate electrode crossing at least a portion of the active fins. The device further includes a plurality of source/drain regions disposed on the active fins adjacent the at least one gate electrode and separated from one another by the at least one non-active fin.

公开(公告)号：US09984925B2

公开(公告)日：2018-05-29

申请号：US15182024

申请日：2016-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Ho Jeon ,  Sang-Su Kim ,  Cheol Kim ,  Yong-Suk Tak ,  Myung-Geun Song ,  Gi-Gwan Park

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.

公开(公告)号：US09831003B2

公开(公告)日：2017-11-28

申请号：US15498855

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/36 ,  G11C29/42 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4078 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US09659669B2

公开(公告)日：2017-05-23

申请号：US14698219

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G06F11/20 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/00 ,  G11C8/06 ,  G11C8/10

CPC classification number: G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US12218193B2

公开(公告)日：2025-02-04

申请号：US17528251

申请日：2021-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hyun Park ,  Kye-hyun Baek ,  Yong-ho Jeon ,  Cheol Kim ,  Sung-il Park ,  Yun-il Lee ,  Hyung-suk Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.

公开(公告)号：US20230059169A1

公开(公告)日：2023-02-23

申请号：US17718795

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Dongmyoung Kim ,  Cheol Kim ,  Dongsuk Shin ,  Woogwan Shim ,  Seung Hun Lee ,  Soonwook Jung

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a source/drain pattern disposed on the active pattern; a channel pattern connected to the source/drain pattern, wherein the channel pattern includes semiconductor patterns stacked on each other and spaced apart from each other; and a gate electrode disposed on the channel pattern and extending in a first direction, wherein the gate electrode includes: a channel neighboring part adjacent to a first sidewall of a first semiconductor pattern of the stacked semiconductor patterns; and a body part spaced apart from the first semiconductor pattern, wherein the channel neighboring part is disposed between the body part and the first semiconductor pattern, wherein the first sidewall of the first semiconductor pattern has a first width, wherein the channel neighboring part has a second width less than the first width. The body part has a third width greater than the second width.

公开(公告)号：USRE49375E1

公开(公告)日：2023-01-17

申请号：US17129109

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-cheol Kim ,  Cheol Kim ,  Jaehun Seo ,  YooJung Lee ,  Kisoo Chang ,  Siyoung Choi

IPC: H01L29/78 ,  H01L29/66

Abstract: Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

公开(公告)号：US20190280087A1

公开(公告)日：2019-09-12

申请号：US16033488

申请日：2018-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hyun Park ,  Kye-hyun Baek ,  Yong-ho Jeon ,  Cheol Kim ,  Sung-il Park ,  Yun-il Lee ,  Hyung-suk Lee

IPC: H01L29/06 ,  H01L27/088

Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.