中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.02 seconds)

    Stacked memory device and method of fabricating same
    2.
    发明授权
    Stacked memory device and method of fabricating same 有权
    堆叠式存储器件及其制造方法

    公开(公告)号：US08665644B2

    公开(公告)日：2014-03-04

    申请号：US13864437

    申请日：2013-04-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chul-Woo Park ,  Hong-Sun Hwang ,  In-Gyu Baek ,  Dong-Hyun Sohn

    IPC: G11C11/34

    CPC classification number: H01L21/77 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/24

    Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.

    Abstract translation: 叠层半导体存储器件包括具有功能电路，多个存储单元阵列层以及至少一个连接层的半导体衬底。 存储单元阵列层堆叠在半导体衬底之上。 连接层堆叠在半导体衬底之上，独立于存储单元阵列层。 连接层将布置在存储单元阵列层上的存储单元选择线电连接到功能电路。

    Three-dimensional semiconductor memory device having compensating data skewing according to interlayer timing delay and method of de-skewing data therein
    4.
    发明授权
    Three-dimensional semiconductor memory device having compensating data skewing according to interlayer timing delay and method of de-skewing data therein 有权
    具有根据层间定时延迟的补偿数据偏移的三维半导体存储器件以及其中的数据失真的方法

    公开(公告)号：US08917564B2

    公开(公告)日：2014-12-23

    申请号：US13937367

    申请日：2013-07-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    IPC: G11C7/00 ,  G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  G11C8/18 ,  G11C13/00 ,  G11C29/02 ,  G11C29/50 ,  G11C7/22

    CPC classification number: G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

    Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

    Abstract translation: 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

    Semiconducotr memory device including non-volatile memory cell array
    7.
    发明授权
    Semiconducotr memory device including non-volatile memory cell array 有权
    半导体存储器件包括非易失性存储单元阵列

    公开(公告)号：US09436545B2

    公开(公告)日：2016-09-06

    申请号：US14165820

    申请日：2014-01-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chi-Sung Oh ,  Chul-Sung Park ,  Sang-Bo Lee ,  Dong-Hyun Sohn

    IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G11C11/00 ,  G11C29/42 ,  G11C29/44 ,  G11C11/4076 ,  G11C11/40 ,  G11C29/04 ,  G11C29/12

    CPC classification number: G06F11/1048 ,  G06F11/16 ,  G11C11/005 ,  G11C11/40 ,  G11C11/4076 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1202 ,  G11C2029/1204

    Abstract: A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

    Abstract translation: 公开了可以使用纠错电路校正错误数据的半导体存储器件。 半导体存储器件可以包括DRAM单元阵列，奇偶校验发生器，非易失性存储单元阵列和纠错电路。 奇偶校验发生器被配置为基于输入数据生成具有至少一个位的第一组奇偶校验位。 非易失性存储单元阵列可以存储对应于输入数据的输入数据和第一组奇偶校验位，并且输出与输入数据相对应的第一数据，以及对应于第一组奇偶校验位的第二组奇偶校验位。 误差校正电路被配置为基于第一数据生成作为校正数据的第二数据。

    Semiconductor memory device having resistive memory cells and method of testing the same
    8.
    发明授权
    Semiconductor memory device having resistive memory cells and method of testing the same 有权
    具有电阻式存储单元的半导体存储器件及其测试方法

    公开(公告)号：US09147500B2

    公开(公告)日：2015-09-29

    申请号：US13945007

    申请日：2013-07-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hye-Jin Kim ,  Hyung-Rok Oh ,  Dong-Seok Kang ,  Dong-Hyun Sohn ,  Sang-Beom Kang ,  Chul-Woo Park ,  Yun-Sang Lee

    IPC: G11C11/00 ,  G11C29/10 ,  G11C11/16 ,  G11C29/32 ,  G11C29/34 ,  G11C29/26

    CPC classification number: G11C29/10 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/32 ,  G11C29/34 ,  G11C2029/2602

    Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

    Abstract translation: 半导体存储器件包括存储单元阵列，模式寄存器组和测试电路。 存储单元阵列包括多个字线，多个位线和多个自旋转移转矩磁阻随机存取存储器（STT-MRAM）单元，每个STT-MRAM单元设置在每个字线的交叉区域 和位线，并且STT-MRAM单元包括磁隧道结（MTJ）元件和单元晶体管。 单元晶体管的栅极耦合到字线，单元晶体管的第一电极通过MTJ元件耦合到位线，并且单元晶体管的第二电极耦合到源极线。 模式寄存器组被配置为设置测试模式，并且测试电路被配置为通过使用模式寄存器集执行测试操作。

Patent Agency Ranking