公开(公告)号：US12213256B2

公开(公告)日：2025-01-28

申请号：US17591734

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwa Kim ,  Junso Pak ,  Heeseok Lee ,  Moonseob Jeong ,  Jisoo Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H05K1/02 ,  H05K1/18 ,  H01L25/065

Abstract: A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.

公开(公告)号：US11854985B2

公开(公告)日：2023-12-26

申请号：US17307037

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejung Choi ,  Heeseok Lee ,  Junghwa Kim

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5383 ,  H01L21/486 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24146

Abstract: A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package.

公开(公告)号：US11764182B2

公开(公告)日：2023-09-19

申请号：US17230192

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun So Pak ,  Junghwa Kim ,  Heeseok Lee ,  Moonseob Jeong

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/24 ,  H01L23/49811 ,  H01L24/20 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24225 ,  H01L2924/01022 ,  H01L2924/01029

Abstract: A semiconductor package may include a semiconductor chip including a chip pad, a redistribution structure including a redistribution insulation layer on the semiconductor chip and first redistribution patterns on a surface of the redistribution insulation layer, a passivation layer covering the first redistribution patterns, an UBM pattern on the passivation layer and extending into an opening of the passivation layer, a second redistribution pattern on the UBM pattern, conductive pillars on the second redistribution pattern, and a package connection terminal on the conductive pillars. The opening in the passivation layer may vertically overlap a portion of each of the first redistribution patterns. The second redistribution pattern may connect some of the first redistribution patterns to each other. Some of the conductive pillars may be connected to one another through the second redistribution pattern. The first redistribution patterns may be connected to the chip pad.

公开(公告)号：US11502061B2

公开(公告)日：2022-11-15

申请号：US16592897

申请日：2019-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsang Cho ,  Heeseok Lee ,  Yunhyeok Im ,  Moonseob Jeong

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

公开(公告)号：US11165143B2

公开(公告)日：2021-11-02

申请号：US16817957

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghwa Kim ,  Heeseok Lee

IPC: H01L23/495 ,  H01Q1/38 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L23/66 ,  H01Q9/04 ,  H01Q9/16

Abstract: An antenna module includes an antenna substrate, a fan-out package and first electrical connection structures. The antenna substrate includes a pattern layer including antenna and ground patterns, and a feeding layer under the pattern layer including a feeding network that supplies power to the antenna patterns. The fan-out package is under the antenna substrate and includes a semiconductor chip driving the antenna substrate, an encapsulant encapsulating some of the semiconductor chip, a first redistribution layer on the semiconductor chip electrically connecting the semiconductor chip with the antenna substrate, and a second redistribution layer under the semiconductor chip electrically connecting the semiconductor chip with external devices. The first electrical connection structures are between and electrically connect the antenna substrate and the fan-out package. A logic layer including logic patterns electrically connecting the pattern layer with the feeding layer in the antenna substrate in the first redistribution layer in the fan-out package.

公开(公告)号：US10211159B2

公开(公告)日：2019-02-19

申请号：US15215227

申请日：2016-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha Jung ,  Jongkook Kim ,  Bona Baek ,  Heeseok Lee ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US09721644B2

公开(公告)日：2017-08-01

申请号：US15207989

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C5/02 ,  G11C11/4093 ,  H01L27/108 ,  H01L25/065 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.