公开(公告)号：US11837577B2

公开(公告)日：2023-12-05

申请号：US17853140

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Kyung Suk Oh ,  Eunseok Song ,  Seung-Yong Cha

IPC: H01L23/528 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L23/528 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

公开(公告)号：US09830973B2

公开(公告)日：2017-11-28

申请号：US15639073

申请日：2017-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C5/02 ,  G11C11/4093 ,  H01L27/108 ,  H01L25/065 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

公开(公告)号：US09659852B2

公开(公告)日：2017-05-23

申请号：US14957053

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsuk Kim ,  HyunJong Moon ,  Tai-Hyun Eum ,  Heeseok Lee ,  Keung Beum Kim ,  Yonghoon Kim ,  Yoonha Jung ,  Seung-Yong Cha

IPC: H01L23/52 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block.

公开(公告)号：US20130313706A1

公开(公告)日：2013-11-28

申请号：US13746853

申请日：2013-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghoon Kim ,  Keung Beum Kim ,  Seongho Shin ,  Seung-Yong Cha ,  Inho Choi

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.

公开(公告)号：US10424571B2

公开(公告)日：2019-09-24

申请号：US15696973

申请日：2017-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn Choi ,  Eun-Seok Song ,  Seung-Yong Cha ,  Yun-Hee Lee

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01F27/28 ,  H01F27/24 ,  H01L25/065 ,  H01F17/00 ,  H01L23/00

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.

公开(公告)号：US20170069369A1

公开(公告)日：2017-03-09

申请号：US15207989

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keung Beum Kim ,  HyunJong Moon ,  Heeseok Lee ,  Seung-Yong Cha

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/408 ,  H01L27/108 ,  H01L25/065

CPC classification number: G11C11/4093 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4096 ,  H01L25/0657 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

Abstract translation: 半导体存储器件包括具有用于管芯端接的第一终端电阻器和第二存储器管芯的第一存储器管芯，具有用于管芯端接的第二终端电阻器并形成在第一存储器管芯上。 第一和第二存储器管芯中的每一个具有中心焊盘类型并且基于多级结构进行操作。 当访问第一存储器管芯时，第二终端电阻器连接到第二存储管芯，并且当访问第二存储器管芯时，第一终端电阻器连接到第一存储器管芯。

公开(公告)号：US20150001715A1

公开(公告)日：2015-01-01

申请号：US14487287

申请日：2014-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoon Kim ,  Keung Beum Kim ,  Seongho Shin ,  Seung-Yong Cha ,  Inho Choi

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.

Abstract translation: 提供一种半导体器件，其包括第一半导体封装，第二半导体封装和连接结构。 第一半导体封装包括第一衬底。 第一基板包括第一区域和第二区域。 第二半导体封装安装在第一半导体封装上。 连接结构电连接第二半导体封装和第一半导体封装。 连接结构包括在第一区域的第一连接图案。 第一连接图案在第一区域提供数据信号。 连接结构还包括在第二区域处的第二连接图案。 第二连接模式在第二区域提供控制/寻址信号。 多个第二连接图案小于第一连接图案的数量。

公开(公告)号：US08866310B2

公开(公告)日：2014-10-21

申请号：US13746853

申请日：2013-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoon Kim ,  Keung Beum Kim ,  Seongho Shin ,  Seung-Yong Cha ,  Inho Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.

Abstract translation: 提供一种半导体器件，其包括第一半导体封装，第二半导体封装和连接结构。 第一半导体封装包括第一衬底。 第一基板包括第一区域和第二区域。 第二半导体封装安装在第一半导体封装上。 连接结构电连接第二半导体封装和第一半导体封装。 连接结构包括在第一区域的第一连接图案。 第一连接图案在第一区域提供数据信号。 连接结构还包括在第二区域处的第二连接图案。 第二连接模式在第二区域提供控制/寻址信号。 多个第二连接图案小于第一连接图案的数量。

公开(公告)号：US11244938B2

公开(公告)日：2022-02-08

申请号：US16554818

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn Choi ,  Eun-Seok Song ,  Seung-Yong Cha ,  Yun-Hee Lee

IPC: H01L25/18 ,  H01L23/538 ,  H01F27/28 ,  H01F27/24 ,  H01L25/065 ,  H01F17/00 ,  H01L23/498 ,  H01L23/00

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.

公开(公告)号：US09799591B2

公开(公告)日：2017-10-24

申请号：US14825831

申请日：2015-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yong Cha ,  Keung Beum Kim ,  Yonghoon Kim ,  HyunJong Moon ,  Heeseok Lee

IPC: H01L23/00 ,  H01L23/50 ,  H01L23/367 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/49827 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/16265 ,  H01L2224/1713 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041

Abstract: A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.