公开(公告)号：US20240119984A1

公开(公告)日：2024-04-11

申请号：US18544996

申请日：2023-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Hong ,  Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: G11C11/402 ,  G11C11/39 ,  H01L27/102 ,  H01L29/66 ,  H01L29/749

CPC classification number: G11C11/4023 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/66363 ,  H01L29/749

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

公开(公告)号：US20240064996A1

公开(公告)日：2024-02-22

申请号：US18170136

申请日：2023-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Ilho Myeong ,  Daewon Ha

IPC: H10B51/20 ,  H10B51/10 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L23/5283 ,  H01L29/516 ,  H01L29/78391

Abstract: A semiconductor device includes first and second cell arrays. The first cell array includes a first gate electrode that extends in a vertical direction, a first channel pattern on a side surface of the first gate electrode, and a first bit line electrically connected to the first channel pattern. The second cell array includes a second gate electrode that extends in the vertical direction, a second channel pattern on a side surface of the second gate electrode, and a second bit line electrically connected to the second channel pattern. A first bit line pad is electrically connected to the first bit line and a second bit line pad is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.

公开(公告)号：US11887986B2

公开(公告)日：2024-01-30

申请号：US17503713

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwon Yoo ,  Yongseok Kim ,  Ilgweon Kim ,  Hyuncheol Kim ,  Hyeoungwon Seo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L27/12 ,  H01L25/065 ,  H01L21/84 ,  H01L27/13 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/13 ,  H01L24/08 ,  H01L2224/08145

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.

公开(公告)号：US11741576B2

公开(公告)日：2023-08-29

申请号：US17207319

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim

IPC: G06T5/00 ,  H04N1/58 ,  H04N9/79 ,  H04N9/64

CPC classification number: G06T5/002 ,  H04N1/58 ,  H04N9/646 ,  H04N9/7908

Abstract: Provided is an operation method of an image signal processor (ISP) configured to perform signal processing on a raw image received from an image device, the operation method including generating a plurality of multi-scale images based on an input image, the plurality of multi-scale images having resolutions that are different from each other, iteratively performing a fast global weighted least squares (FGWLS) based operation on each of the plurality of multi-scale images to generate a final illuminance map, and outputting an enhanced image based on the final illuminance map and the input image.

公开(公告)号：US11647625B2

公开(公告)日：2023-05-09

申请号：US17191308

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Hong ,  Kyunghwan Lee ,  Hyuncheol Kim ,  Huijung Kim ,  Hyunmog Park ,  Kiseok Lee ,  Minhee Cho

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/24

CPC classification number: H01L27/1082 ,  G11C5/063 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/24

Abstract: A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.

公开(公告)号：US11508730B2

公开(公告)日：2022-11-22

申请号：US17032040

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Jaeho Hong

IPC: H01L27/108 ,  G11C7/18

Abstract: Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

公开(公告)号：US11342436B2

公开(公告)日：2022-05-24

申请号：US16801508

申请日：2020-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Hong ,  Yongseok Kim ,  Hyuncheol Kim ,  Seokhan Park ,  Satoru Yamada ,  Kyunghwan Lee

IPC: H01L29/51 ,  H01L29/423 ,  H01L27/108 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.

公开(公告)号：US11284444B2

公开(公告)日：2022-03-22

申请号：US16772963

申请日：2018-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonghyeuk Lee ,  Hyuncheol Kim ,  Soongyoon Choi

IPC: H04W74/08 ,  H04W56/00 ,  H04L7/10 ,  H04L7/00 ,  H04W88/08

Abstract: The present disclosure relates to a method and apparatus for transmitting and receiving signals in a wireless communication system. According to an embodiment of the present disclosure, random access signals including preamble sequences transmitted from a user equipment (UE) may be detected during a plurality of observation periods. A temporary timing advance (TA) value may be determined based on a preamble sequence of a random access signal having greater signal strength among the plurality of random access signals detected in the plurality of observation periods. A final TA value may be acquired based on the temporary TA value according to a result of comparison between the strengths of the random access signals received in the plurality of observation periods and a preset threshold value. A random access response signal including the final TA value may be transmitted to the UE.

公开(公告)号：US12284128B2

公开(公告)日：2025-04-22

申请号：US17625995

申请日：2020-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjae Lee ,  Hyuncheol Kim

IPC: H04W4/00 ,  H04L5/00

Abstract: Disclosed is a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system, such as long term evolution (LTE). The purpose of the disclosure is to detect interference between base stations in a wireless communication system, and a base station operating method can comprise the steps of: receiving signals through a resource allocated for reference signals (RSs) for interference measurement; detecting at least one RS on the basis of the signals; and determining that at least one among the RSs has been received on the basis of cross-correlation values between candidate RSs.

公开(公告)号：US12193343B2

公开(公告)日：2025-01-07

申请号：US17192093

申请日：2021-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H10N70/00 ,  H01L29/423 ,  H10B63/00

Abstract: A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.