公开(公告)号：US11935597B2

公开(公告)日：2024-03-19

申请号：US17523337

申请日：2021-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/10 ,  G11C16/26 ,  H01L23/481 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US11901321B2

公开(公告)日：2024-02-13

申请号：US17854287

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Byungchul Jang ,  Joonsung Lim

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  G06F11/10 ,  H01L25/00 ,  G11C7/10 ,  H10B41/20 ,  H10B41/40 ,  H10B41/50 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L24/08 ,  G06F11/1008 ,  G06F11/1048 ,  G11C7/10 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/20 ,  H10B41/40 ,  H10B41/50 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H01L2224/0603 ,  H01L2224/08145 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.

公开(公告)号：US20220399369A1

公开(公告)日：2022-12-15

申请号：US17743738

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoon Son ,  Junhyoung Kim ,  Joonsung Lim

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and extending by different lengths in a second direction on the second region to have pad regions in which upper surfaces thereof are exposed, channel structures penetrating the gate electrodes, extending in the first direction, and respectively including a channel layer, on the first region, contact plugs penetrating the pad regions of the gate electrodes and extending in the first direction, and contact insulating layers surrounding the contact plugs. The gate electrodes have side surfaces protruding further toward the contact plugs in the pad regions than ones of the gate electrodes therebelow.