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公开(公告)号：US20230367672A1
公开(公告)日：2023-11-16
申请号：US18226622
申请日：2023-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Kijun Lee , Myungkyu Lee , Yeonggeol Song , Jinhoon Jang , Sunghye Cho , Isak Hwang
IPC: G06F11/10
CPC classification number: G06F11/1068
Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.
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公开(公告)号：US20230168819A1
公开(公告)日：2023-06-01
申请号：US17842981
申请日：2022-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeonggeol Song , Sungrae Kim , Kijun Lee , Myungkyu Lee , Eunae Lee , Sunghye Cho
CPC classification number: G06F3/0626 , G06F3/064 , G06F3/0679 , G06F11/1068
Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.
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公开(公告)号：US11269723B2
公开(公告)日：2022-03-08
申请号：US16988931
申请日：2020-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sanguhn Cha , Kijun Lee , Myungkyu Lee , Sunghye Cho
Abstract: A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.
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公开(公告)号：US11170868B2
公开(公告)日：2021-11-09
申请号：US16864787
申请日：2020-05-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yesin Ryu , Sanguhn Cha , Sunghye Cho , Kijun Lee , Myungkyu Lee , Youngcheon Kwon , Jaeyoun Youn
Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.
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公开(公告)号：US20210208967A1
公开(公告)日：2021-07-08
申请号：US16988931
申请日：2020-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANGUHN CHA , Kijun Lee , Myungkyu Lee , Sunghye Cho
Abstract: A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.
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Patent Agency Ranking
26.发明申请ERROR CORRECTION DECODER AND OPERATION METHOD OF THE ERROR CORRECTION DECODER 有权错误校正解码器的错误校正解码器和错误校正解码器的操作方法公开(公告)号：US20160103735A1
公开(公告)日：2016-04-14
申请号：US14877448
申请日：2015-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kijun LEE , Myungkyu Lee , Sejin Lim , Junjin Kong
CPC classification number: H03M13/3715 , H03M13/1525 , H03M13/1545 , H03M13/157
Abstract: The inventive concepts relate to an operation method of an error correction decoder correcting an error of data read from a nonvolatile memory. The operation method may include receiving the data from the nonvolatile memory, performing a first error correction with respect to the received data in a simplified mode, and performing, when the first error correction fails in the simplified mode, a second error correction with respect to the received data in a full mode. When the first error correction of the simplified mode is performed, a part of operations of the second error correction of the full mode may be omitted.
Abstract translation: 本发明构思涉及纠错解码器校正从非易失性存储器读取的数据的错误的操作方法。 操作方法可以包括从非易失性存储器接收数据，以简化模式对接收到的数据执行第一纠错，并且当在简化模式中第一错误校正失败时执行相对于 接收到的数据处于完整模式。 当执行简化模式的第一纠错时，可以省略完整模式的第二纠错的一部分操作。
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公开(公告)号：US12212339B2
公开(公告)日：2025-01-28
申请号：US17984430
申请日：2022-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myungkyu Lee , Kijun Lee , Sunghye Cho , Sungrae Kim
Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.
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公开(公告)号：US20240281323A1
公开(公告)日：2024-08-22
申请号：US18469894
申请日：2023-09-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myungkyu Lee , Seongmuk Kang , Jiho Kim , Kijun Lee , Kyomin Sohn
IPC: G06F11/10
CPC classification number: G06F11/1044
Abstract: A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip includes an error correction code (ECC) engine, the ECC engine including an ECC decoder to correct Q symbols errors in a codeword set read from the memory module, Q is a maximum natural number equal to or less than P and P is a natural number equal to or greater than four. The ECC decoder is configured to generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix and to perform a first ECC decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols.
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公开(公告)号：US12057184B2
公开(公告)日：2024-08-06
申请号：US18164100
申请日：2023-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunghye Cho , Kiheung Kim , Sungrae Kim , Junhyung Kim , Kijun Lee , Myungkyu Lee , Changyong Lee , Sanguhn Cha
IPC: G11C29/42 , G11C11/408 , G11C11/4091 , G11C29/44 , G11C29/12
CPC classification number: G11C29/42 , G11C11/4087 , G11C11/4091 , G11C29/4401 , G11C2029/1202 , G11C2029/1204
Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.
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公开(公告)号：US11815997B2
公开(公告)日：2023-11-14
申请号：US17814964
申请日：2022-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Suhun Lim , Kijun Lee , Myungkyu Lee , Eunchul Kwon , Hoyoun Kim , Jongmin Lee
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F17/16 , H03M13/1575
Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.
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