公开(公告)号：US10686069B2

公开(公告)日：2020-06-16

申请号：US16028083

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin Hye Kim ,  Kyung Seok Oh ,  Gu Young Cho ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L29/10 ,  H01L23/532 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768

Abstract: A semiconductor device includes a substrate and a plurality of semiconductor fins protruding from the substrate. Source/drain regions are disposed at tops of respective ones of the semiconductor fins, each having a width greater than a width of individual ones of the semiconductor fins. A gate electrode is disposed on side surfaces of the semiconductor fins below the source/drain regions. Insulating layers contact the side surfaces of the semiconductor fins and cover upper surfaces of the gate electrode.

公开(公告)号：US10580736B2

公开(公告)日：2020-03-03

申请号：US16441433

申请日：2019-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Yeol Kim ,  Ji Won Kang ,  Chung Hwan Shin ,  Jin Il Lee ,  Sang Jin Hyun

IPC: H01L21/285 ,  H01L23/532 ,  H01L23/528 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  B24B37/04 ,  H01L21/768 ,  H01L21/321 ,  C23C16/455 ,  H01L23/485

Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.

公开(公告)号：US10557198B2

公开(公告)日：2020-02-11

申请号：US16190558

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Dong Woo Kim ,  Jun Ki Park ,  Sang Yub Ie ,  Sang Jin Hyun

IPC: H01L21/285 ,  C23C16/455

Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a substrate chuck, a shower head structure over the substrate chuck, and a gas distribution apparatus connected to the shower head structure. The gas distribution apparatus includes a dispersion container including a first dispersion space and a gas inlet section on the dispersion container. The gas inlet section includes a first inlet pipe including a first inlet path fluidly connected to the first dispersion space and a second inlet pipe including a second inlet path fluidly connected to the first dispersion space. The second inlet pipe surrounds at least a portion of a sidewall of the first inlet pipe.

公开(公告)号：US20190280116A1

公开(公告)日：2019-09-12

申请号：US16426819

申请日：2019-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Soo Kim ,  Dong Hyun Roh ,  Koung Min Ryu ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

公开(公告)号：US10177149B2

公开(公告)日：2019-01-08

申请号：US15452203

申请日：2017-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk Chai ,  Sang Yong Kim ,  Hoon Joo Na ,  Sang Jin Hyun

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US10128245B2

公开(公告)日：2018-11-13

申请号：US15473031

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Sun Lee ,  Joon Gon Lee ,  Na Rae Kim ,  Chul Sung Kim ,  Do Hyun Lee ,  Ryuji Tomita ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/165 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.

公开(公告)号：US11967595B2

公开(公告)日：2024-04-23

申请号：US17038964

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk Chai ,  Sang Yong Kim ,  Hoon Joo Na ,  Sang Jin Hyun

IPC: H01L27/092 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7845

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US11600518B2

公开(公告)日：2023-03-07

申请号：US17308128

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo Kim ,  Chae Ho Na ,  Gyu Hwan Ahn ,  Dong Hyun Roh ,  Sang Jin Hyun

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.

公开(公告)号：US11296196B2

公开(公告)日：2022-04-05

申请号：US16695675

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US11018050B2

公开(公告)日：2021-05-25

申请号：US16386704

申请日：2019-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo Kim ,  Chae Ho Na ,  Gyu Hwan Ahn ,  Dong Hyun Roh ,  Sang Jin Hyun

IPC: H01L29/66 ,  H01L21/762 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.