公开(公告)号：US12249505B2

公开(公告)日：2025-03-11

申请号：US18513297

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Dongwoo Kim ,  Jihye Yi ,  Jinbum Kim ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

公开(公告)号：US12159911B2

公开(公告)日：2024-12-03

申请号：US17552446

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Jinbum Kim ,  Dongwoo Kim ,  Dongsuk Shin ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L29/41 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode provided on the channel pattern and extended in a first direction, and an active contact coupled to the source/drain pattern. The active contact includes a buried portion buried in the source/drain pattern and a contact portion on the buried portion. The buried portion includes an expansion portion provided in a lower portion of the source/drain pattern and a vertical extension portion connecting the contact portion to the expansion portion.

公开(公告)号：US11888028B2

公开(公告)日：2024-01-30

申请号：US17862453

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US11887617B2

公开(公告)日：2024-01-30

申请号：US17260684

申请日：2019-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Hoon Shin ,  Jonguk Yoo ,  Sangmoon Lee

IPC: G10L21/0216 ,  G10L21/0272 ,  G10L25/18 ,  G10L25/60

CPC classification number: G10L21/0216 ,  G10L21/0272 ,  G10L25/18 ,  G10L25/60 ,  G10L2021/02166

Abstract: An electronic device for speech recognition includes a multi-channel microphone array required for remote speech recognition. The electronic device improves efficiency and performance of speech recognition of the electronic device in a space where noise other than speech to be recognized exists. A control method includes receiving a plurality of audio signals output from a plurality of sources through a plurality of microphones and analyzing the audio signals and obtaining information on directions in which the audio signals are input and information on input times of the audio signals. A target source for speech recognition among the plurality of sources is determined on the basis of the obtained information on the directions in which the plurality of audio signals are input, and the obtained information on the input times of the plurality of audio signals, and an audio signal obtained from the determined target source is processed.

公开(公告)号：US11749754B2

公开(公告)日：2023-09-05

申请号：US17550712

申请日：2021-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon Lee ,  Kyungin Choi ,  Seunghun Lee

IPC: H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6681

Abstract: An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

公开(公告)号：US11631670B2

公开(公告)日：2023-04-18

申请号：US17509239

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Kim ,  Jihye Lee ,  Sangmoon Lee ,  Seung Hun Lee

IPC: H01L27/092 ,  H01L29/161

Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.

公开(公告)号：US11380541B2

公开(公告)日：2022-07-05

申请号：US17006799

申请日：2020-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Dongwoo Kim ,  Jihye Yi ,  JinBum Kim ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L23/532 ,  H01L23/485 ,  H01L29/10 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L21/28

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

公开(公告)号：US11233151B2

公开(公告)日：2022-01-25

申请号：US16887900

申请日：2020-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon Lee ,  Kyungin Choi ,  Seunghun Lee

IPC: H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

Abstract: An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

公开(公告)号：US11201087B2

公开(公告)日：2021-12-14

申请号：US16838089

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Seung Hun Lee ,  Dahye Kim ,  Ilgyou Shin ,  Sangmoon Lee ,  Kyungin Choi

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762

Abstract: A method includes forming an active pattern on a substrate, the active pattern comprising first semiconductor patterns and second semiconductor patterns, which are alternately stacked, forming a capping pattern on a top surface and a sidewall of the active pattern, performing a deposition process on the capping pattern to form an insulating layer, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer. The capping pattern has a crystalline structure and is in physical contact with sidewalls of the first semiconductor patterns and sidewalls of the second semiconductor patterns.

公开(公告)号：US11171224B2

公开(公告)日：2021-11-09

申请号：US16889899

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan Suh ,  Sangmoon Lee ,  Yihwan Kim ,  Woo Bin Song ,  Dongsuk Shin ,  Seung Ryul Lee

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.