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    METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
    21.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20200098716A1

    公开(公告)日：2020-03-26

    申请号：US16698117

    申请日：2019-11-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youn Ji MIN ,  Seokhyun LEE ,  Jongyoun KIM ,  Kyoung Lim SUK ,  SeokWon LEE

    IPC: H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

    Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
    25.
    发明公开
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240063236A1

    公开(公告)日：2024-02-22

    申请号：US18195618

    申请日：2023-05-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seokhyun LEE

    IPC: H01L27/146

    CPC classification number: H01L27/14618 ,  H01L27/14689 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14627

    Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution layer having an opening on a transparent plate, the first redistribution layer including first redistribution wirings; forming a plurality of conductive structures that extend in a vertical direction on the first redistribution layer and are electrically connected to the first redistribution wirings; providing an image sensor chip comprising a lens, and providing a plurality of conductive members; disposing the image sensor chip on the first redistribution layer such that the lens faces the opening and the conductive members are electrically connected to the first redistribution wirings; forming an adhesive member that extends along the peripheral region and surrounds the conductive members; forming a sealing member on the first redistribution layer to cover the image sensor chip, the conductive structures, and the adhesive member; and forming a second redistribution layer.

    SEMICONDUCTOR PACKAGE
    26.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220406702A1

    公开(公告)日：2022-12-22

    申请号：US17892215

    申请日：2022-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokhyun LEE ,  Jongyoun KIM ,  Yeonho JANG ,  Jaegwon JANG

    IPC: H01L23/498 ,  H01L21/48

    Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

    SEMICONDUCTOR PACKAGE
    27.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220077066A1

    公开(公告)日：2022-03-10

    申请号：US17215517

    申请日：2021-03-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongyoun KIM ,  Seokhyun LEE ,  Gwangjae JEON

    IPC: H01L23/538 ,  H01L23/00

    Abstract: A semiconductor package includes a redistribution substrate having a semiconductor chip mounted on a top surface thereof with and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate includes a first redistribution pattern on a bottom surface of the connection terminal and comprising a first via and a first interconnection on the first via, a pad pattern between the first redistribution pattern and the connection terminal and comprising a pad via and a pad on the pad via, and a second redistribution pattern between the first redistribution pattern and the pad pattern and comprising a second via and a second interconnection on the second via with a recess region where a portion of a top surface of the second interconnection is recessed. A bottom surface of the recess region is located at a lower level than a topmost surface of the second interconnection.

    METHOD OF MANUFACTURING REDISTRIBUTION SUBSTRATE
    28.
    发明申请
    METHOD OF MANUFACTURING REDISTRIBUTION SUBSTRATE 有权

    公开(公告)号：US20210296163A1

    公开(公告)日：2021-09-23

    申请号：US17341510

    申请日：2021-06-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seokhyun LEE

    IPC: H01L21/768 ,  H01L49/02

    Abstract: A redistribution substrate includes a first conductive pattern including a first lower pad and a second lower pad, the first and second lower pads being within a first insulating layer, a second conductive pattern including a first upper pad and a second upper pad, the first and second upper pads being on the first insulating layer, a first via connecting the first lower pad and the first upper pad to each other in the first insulating layer, a second via connecting the second lower pad and the second upper pad to each other in the first insulating layer, and a capacitor between the first lower pad and the first via.

    METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
    30.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190035756A1

    公开(公告)日：2019-01-31

    申请号：US15867075

    申请日：2018-01-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUN JI MIN ,  Seokhyun LEE ,  Jongyoun KIM ,  Kyoung Lim SUK ,  SeokWon LEE

    IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

    Abstract: A method of fabricating a semiconductor package including, forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.

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