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    Semiconductor memory devices and methods of forming the same
    23.
    发明授权
    Semiconductor memory devices and methods of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US09466612B2

    公开(公告)日：2016-10-11

    申请号：US14985730

    申请日：2015-12-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    IPC: H01L29/76 ,  H01L27/115 ,  H01L29/792 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324

    CPC classification number: H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

    Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中，该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中，该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外，该方法可以包括在第二通过区域中形成第二半导体层。

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME
    24.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
    半导体存储器件及其形成方法

    公开(公告)号：US20160118400A1

    公开(公告)日：2016-04-28

    申请号：US14985730

    申请日：2015-12-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    IPC: H01L27/115 ,  H01L21/306 ,  H01L21/324

    CPC classification number: H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

    Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中，该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中，该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外，该方法可以包括在第二通过区域中形成第二半导体层。

    METHOD AND APPARATUS FOR MANAGING DATA IN NEAR FIELD COMMUNICATION SYSTEM
    26.
    发明申请
    METHOD AND APPARATUS FOR MANAGING DATA IN NEAR FIELD COMMUNICATION SYSTEM 审中-公开
    用于管理近场通信系统中的数据的方法和装置

    公开(公告)号：US20140242909A1

    公开(公告)日：2014-08-28

    申请号：US14187808

    申请日：2014-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Doyoung Kim ,  Dongkeon Kong ,  Dongwoo Kim ,  Jeongje Park ,  Kwanghyeon Lee ,  Naehyun Lim ,  Hyoungkyu Lim ,  Yong Chang

    IPC: H04B5/00

    CPC classification number: H04W48/02 ,  H04L63/105 ,  H04L69/22 ,  H04W4/80 ,  H04W8/22 ,  H04W12/08

    Abstract: A data managing method of a terminal in a Near Field Communication (NFC) system. The data managing method includes setting up an NFC link with a server; transmitting to the server, a request message including access level information of the terminal; and receiving from the server, a response message that classifies whether data access is allowed or restricted, based on an access level of the terminal, wherein the access level information of the terminal is included in a header of the request message.

    Abstract translation: 近场通信（NFC）系统中的终端的数据管理方法。 数据管理方法包括与服务器建立NFC链路; 向所述服务器发送包括所述终端的访问级别信息的请求消息; 以及基于所述终端的访问级别，从所述服务器接收分类数据访问是否被允许或限制的响应消息，其中，所述终端的访问级别信息被包括在所述请求消息的报头中。

    Method for providing HDR image and electronic device supporting the same
    27.
    发明授权
    Method for providing HDR image and electronic device supporting the same 有权

    公开(公告)号：US12288316B2

    公开(公告)日：2025-04-29

    申请号：US17672110

    申请日：2022-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chansik Park ,  Dongwoo Kim ,  Jeehong Kim ,  Wonjun Roh ,  Hyuntaek Lee ,  Donghyun Yeom

    IPC: G06T5/92

    Abstract: A method and electronic device are provided for providing a high dynamic range (HDR) image. The HDR image is obtained. A first area, in which the HDR image is displayed, and a second area, in which an image is displayed, are identified within a screen. The first area is white point-processed based on a first white point, and the second are is white point-processed based on a second white point that is set for a display of the electronic device and different from the first white point. The screen including the white point-processed first area and the white point-processed second area is displayed on the display.

    SEMICONDUCTOR DEVICES
    28.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240258410A1

    公开(公告)日：2024-08-01

    申请号：US18531836

    申请日：2023-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongwoo Kim ,  Jinbum Kim

    IPC: H01L29/732 ,  H01L23/528 ,  H01L29/66

    CPC classification number: H01L29/7325 ,  H01L23/5286 ,  H01L29/66287

    Abstract: A semiconductor device includes a substrate having a recessed region, a first semiconductor region including a first semiconductor layer on a bottom surface and an inner side surface of the recessed region and a first protrusion on the first semiconductor layer, and having a first conductivity type, a second semiconductor region including a second semiconductor layer on the first semiconductor layer and a second protrusion on the second semiconductor layer, and having a second conductivity type, a third semiconductor region including a third semiconductor layer on the second semiconductor layer and a third protrusion on the third semiconductor layer, and having the first conductivity type, a epitaxial stopper layer covering the bottom surface of the recessed region between the first semiconductor region and the substrate and including a material different from materials of the first semiconductor region, and a dummy gate structure intersecting the first to third protrusions on the substrate.

    Semiconductor device with source/drain pattern including buffer layer
    29.
    发明授权
    Semiconductor device with source/drain pattern including buffer layer 有权

    公开(公告)号：US12027596B2

    公开(公告)日：2024-07-02

    申请号：US18201308

    申请日：2023-05-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ryong Ha ,  Dongwoo Kim ,  Gyeom Kim ,  Yong Seung Kim ,  Pankwi Park ,  Seung Hun Lee

    IPC: H01L29/417 ,  H01L29/10 ,  H01L29/423

    CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

    Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

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