公开(公告)号：US20180166463A1

公开(公告)日：2018-06-14

申请号：US15893157

申请日：2018-02-09

Applicant: SanDisk Technologies LLC

Inventor： Hoon Cho ,  Jun Wan ,  Ching-Huang Lu

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/788 ,  H01L29/423 ,  H01L29/40 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/408 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/788 ,  H01L29/792

Abstract: Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.

公开(公告)号：US09899410B1

公开(公告)日：2018-02-20

申请号：US15376925

申请日：2016-12-13

Applicant: SanDisk Technologies LLC

Inventor： Hoon Cho ,  Jun Wan ,  Ching-Huang Lu

IPC: H01L29/792 ,  H01L31/119 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/40 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/408 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/788 ,  H01L29/792

Abstract: Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.

公开(公告)号：US12046279B2

公开(公告)日：2024-07-23

申请号：US17751179

申请日：2022-05-23

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Jun Wan ,  Bo Lei

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

公开(公告)号：US20230377643A1

公开(公告)日：2023-11-23

申请号：US17751179

申请日：2022-05-23

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Jun Wan ,  Bo Lei

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10

Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

公开(公告)号：US10007311B2

公开(公告)日：2018-06-26

申请号：US15237139

申请日：2016-08-15

Applicant: SanDisk Technologies LLC

Inventor： Deepak Raghu ,  Pao-Ling Koh ,  Philip Reusswig ,  Chris Nga Yee Yip ,  Jun Wan ,  Yan Li

IPC: G11C7/04 ,  G06F1/20 ,  G06F3/06

CPC classification number: G06F1/206 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0616 ,  G06F3/0653 ,  G06F3/0688 ,  Y02D10/14

Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.