公开(公告)号：US20230267981A1

公开(公告)日：2023-08-24

申请号：US17677666

申请日：2022-02-22

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Thomas Trent ,  Nathan Franklin ,  Michael Grobis ,  James W. Reiner ,  Hans Jurgen Richter ,  Michael Nicolas Albert Tran

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/72

Abstract: Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor which improves read margin. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector. Reducing Ihold of the threshold switching selector improves read margin.

公开(公告)号：US11682442B2

公开(公告)日：2023-06-20

申请号：US17846678

申请日：2022-06-22

Applicant: SanDisk Technologies LLC

Inventor： Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L27/24

CPC classification number: G11C11/1659 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  G11C11/1697 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L27/2481

Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

公开(公告)号：US20230005530A1

公开(公告)日：2023-01-05

申请号：US17939826

申请日：2022-09-07

Applicant: SanDisk Technologies LLC

Inventor： Nathan Franklin ,  Ward Parkinson ,  Michael Grobis ,  James O'Toole

IPC: G11C11/56 ,  H01L23/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L25/065

Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

公开(公告)号：US20220415387A1

公开(公告)日：2022-12-29

申请号：US17939818

申请日：2022-09-07

Applicant: SanDisk Technologies LLC

Inventor： Nathan Franklin ,  Ward Parkinson ,  Michael Grobis ,  James O'Toole

IPC: G11C11/56 ,  H01L23/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L25/065

Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

公开(公告)号：US20220335999A1

公开(公告)日：2022-10-20

申请号：US17846684

申请日：2022-06-22

Applicant: SanDisk Technologies LLC

Inventor： Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin

IPC: G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

公开(公告)号：US11386945B2

公开(公告)日：2022-07-12

申请号：US17061636

申请日：2020-10-02

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Nathan Franklin ,  Thomas Trent

IPC: G11C11/16 ,  H01L43/02

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

公开(公告)号：US11328759B2

公开(公告)日：2022-05-10

申请号：US17061626

申请日：2020-10-02

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Nathan Franklin ,  Thomas Trent

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.

公开(公告)号：US20220108739A1

公开(公告)日：2022-04-07

申请号：US17061626

申请日：2020-10-02

Applicant: SanDisk Technologies LLC

Inventor： Ward Parkinson ,  James O'Toole ,  Nathan Franklin ,  Thomas Trent

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.

公开(公告)号：US10545692B2

公开(公告)日：2020-01-28

申请号：US15945699

申请日：2018-04-04

Applicant: SanDisk Technologies LLC

Inventor： Nathan Franklin ,  Ward Parkinson

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for memory maintenance operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to perform one or more maintenance operations on a non-volatile memory medium during a predefined period of time after receiving a refresh command.