中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

26 records (took 0.03 seconds)

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LOW-K DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME
    21.
    发明公开
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LOW-K DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240064985A1

    公开(公告)日：2024-02-22

    申请号：US18386456

    申请日：2023-11-02

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Masanori Tsutsumi ,  Kazuki Isozumi ,  Peng Zhang

    IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

    CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The electrically conductive layers include word-line-level electrically conductive layers and drain-select-level electrically conductive layers overlying the word-line-level electrically conductive layers. An array of memory opening fill structures is located within an array of memory openings vertically extending through the alternating stack. An encapsulated cavity vertically extends through the drain-select-level electrically conductive layers. The array of memory opening fill structures includes two rows of first memory opening fill structures that are arranged along a first horizontal direction. Each of the first memory opening fill structures includes a respective planar straight sidewall in contact with a respective portion of a pair of straight sidewalls of the encapsulated cavity.

    NON-VOLATILE MEMORY WITH ONE SIDED PHASED RAMP DOWN AFTER PROGRAM-VERIFY
    22.
    发明公开
    NON-VOLATILE MEMORY WITH ONE SIDED PHASED RAMP DOWN AFTER PROGRAM-VERIFY 审中-公开

    公开(公告)号：US20240029806A1

    公开(公告)日：2024-01-25

    申请号：US17872148

    申请日：2022-07-25

    Applicant: SanDisk Technologies LLC

    Inventor： Jiacen Guo ,  Peng Zhang ,  Xiang Yang ,  Yanli Zhang

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/08 ,  G11C16/24 ,  G11C16/0483

    Abstract: In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.

    Bi-directional sensing in a memory
    23.
    发明授权
    Bi-directional sensing in a memory 有权

    公开(公告)号：US11423993B2

    公开(公告)日：2022-08-23

    申请号：US16676023

    申请日：2019-11-06

    Applicant: SanDisk Technologies LLC

    Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Peng Zhang ,  Dengtao Zhao ,  Deepanshu Dutta

    IPC: G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04

    Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

Patent Agency Ranking