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    NON-VOLATILE MEMORY WITH ADAPTING ERASE PROCESS
    21.
    发明公开
    NON-VOLATILE MEMORY WITH ADAPTING ERASE PROCESS 审中-公开

    公开(公告)号：US20240319905A1

    公开(公告)日：2024-09-26

    申请号：US18358661

    申请日：2023-07-25

    Applicant: SanDisk Technologies LLC

    Inventor： Longju Liu ,  Yi Song ,  Sarath Puthenthermadam ,  Jiahui Yuan

    IPC: G06F3/06

    CPC classification number: G06F3/0652 ,  G06F3/0619 ,  G06F3/0679

    Abstract: A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.

    Non-volatile memory with programmable resistance non-data word line
    22.
    发明授权
    Non-volatile memory with programmable resistance non-data word line 有权

    公开(公告)号：US12099728B2

    公开(公告)日：2024-09-24

    申请号：US17955018

    申请日：2022-09-28

    Applicant: SanDisk Technologies LLC

    Inventor： Towhidur Razzak ,  Ravi Kumar ,  Abu Naser Zainuddin ,  Jiahui Yuan

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0679

    Abstract: In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be lower. To address the word line dependency, the dummy memory cells connected to the dummy word line can be programmed to different threshold voltages based on which data word line is to be programmed. Thus, prior to programming data non-volatile memory cells connected to a particular data word line, the dummy memory cells are programmed to a threshold voltage that is chosen based on the position of the particular data word line.

    Low power mode with read sequence adjustment
    25.
    发明授权
    Low power mode with read sequence adjustment 有权

    公开(公告)号：US12057157B2

    公开(公告)日：2024-08-06

    申请号：US17690332

    申请日：2022-03-09

    Applicant: SanDisk Technologies LLC

    Inventor： Jiahui Yuan ,  Kai Kirk ,  Yu-Chung Lien

    IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

    CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

    Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine whether the apparatus is in low power mode; in response to determining that the apparatus is in low power mode, perform a normal order read operation on a set of memory cells of the plurality of memory cells; and in response to determining that the apparatus is not in low power mode, perform a reverse order read operation on the set of memory cells of the plurality of memory cells.

    Dummy cell resistance tuning in NAND strings
    27.
    发明授权
    Dummy cell resistance tuning in NAND strings 有权

    公开(公告)号：US11935593B2

    公开(公告)日：2024-03-19

    申请号：US17824143

    申请日：2022-05-25

    Applicant: SanDisk Technologies LLC

    Inventor： Yi Song ,  Jiahui Yuan ,  Xiang Yang

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28

    CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28

    Abstract: An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation to program data memory cells. The control circuit is configured to apply a second dummy word line voltage to the one or more dummy word lines in a read operation to read the data memory cells.

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